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24 Commits

Author SHA1 Message Date
Kevin Enderby
044be39090 Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it does 
not get an "Unknown immediate size" assert failure when used.  All instructions 
of this form have an 8-bit immediate.  Also added a test case of an example
instruction that is of this form.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99435 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-24 22:28:42 +00:00
Sean Callanan
cebe955779 Added the rdtscp instruction to the x86 instruction 
tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96073 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 02:06:11 +00:00
Chris Lattner
a599de2410 remove special cases for vmlaunch, vmresume, vmxoff, and swapgs 
fix swapgs to be spelled right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96058 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 00:41:14 +00:00
Chris Lattner
a0331199fc enhance the immediate field encoding to know whether the immediate 
is pc relative or not, mark call and branches as pcrel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96026 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 22:27:07 +00:00
Chris Lattner
0d8db8e0a8 add a bunch of mod/rm encoding types for fixed mod/rm bytes. 
This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95960 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 02:06:33 +00:00
Sean Callanan
108934c65d Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 00:01:26 +00:00
Nate Begeman
ed748a0677 PR 5245 - The imediate size target flag was not set on 3A-prefixed SSSE3 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84506 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 17:31:16 +00:00
Sean Callanan
76f14be685 Modified the Intel instruction tables to include 
versions of CALL and JMP with segmented addresses
provided in-line, as pairs of immediates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81818 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-15 00:35:17 +00:00
Eric Christopher
b120ab4057 Implement sse4.2 string/text processing instructions: 
Add patterns and instruction encoding information.
Add custom lowering to deal with hardwired return register of
uncertain type (xmm0).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79377 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-18 22:50:32 +00:00
Eric Christopher
b4dc13cab7 Add crc32 instruction and intrinsics. Add a new class of prefix 
bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.

New test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78508 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 21:55:08 +00:00
Anton Korobeynikov
ef93cecd80 Add ability to override segment (mostly for code emitter purposes). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57380 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-11 19:09:15 +00:00
Bill Wendling
1dd0086b06 Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the 
SSE2 registers as well as the MMX registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55436 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-27 21:32:04 +00:00
Bill Wendling
cb3c51a4ae Nevermind. This broke the bootstrap (?!). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55318 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 18:32:39 +00:00
Bill Wendling
51e05e7a99 MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these 
instructions on having SSE2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55317 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 18:20:52 +00:00
Anton Korobeynikov
017c260944 Provide a 64 bit variant of mmx.maskmovq intrinsic lowering. 
Is there way to avoid explicit target check?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55238 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-23 15:53:19 +00:00
Dan Gohman
1e684cf1ef Fix comment spacing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55047 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 13:46:21 +00:00
Nate Begeman
30a0de94e7 SSE codegen for vsetcc nodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53719 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-17 16:51:19 +00:00
Evan Cheng
172b794cd5 Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48360 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-14 07:39:27 +00:00
Andrew Lenharth
ea7da50e5a Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47795 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-03-01 13:37:02 +00:00
Nate Begeman
cdd1eeca2c SSE4.1 64b integer insert/extract pattern support 
Move formats into the formats file


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47035 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-02-12 22:51:28 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-29 20:36:04 +00:00
Evan Cheng
700a0fba97 Fix JIT encoding for CMPSD as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45268 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-20 19:57:09 +00:00
Chris Lattner
d7610e16fc Fix the JIT encoding of cmp*ss, which aborts with this assertion currently: 
X86CodeEmitter.cpp:378: failed assertion `0 && "Immediate size not set!"'

I *think* this is right, but Evan, please verify.  It also looks like
CMPSDrr and maybe others are missing this info.  Evan, plz investigate.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45074 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-16 20:12:41 +00:00
Evan Cheng
c64a1a921c Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40628 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-31 08:04:03 +00:00