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409 Commits

Author SHA1 Message Date
Akira Hatanaka
2bd7e532b4 Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158413 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-13 19:06:08 +00:00
Akira Hatanaka
777a120285 Implement fastcc calling convention for MIPS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158410 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-13 18:06:00 +00:00
Akira Hatanaka
94ccee2222 Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node is 
inserted after the shift-left-logical node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157937 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-04 17:46:29 +00:00
Hans Wennborg
70a07c7fc4 MIPS TLS: use the model selected by TargetMachine::getTLSModel(). 
This was mostly done already in r156162, but I missed one place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157929 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-04 14:02:08 +00:00
Chris Lattner
00edc3dea2 remove an unused variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157872 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 01:03:42 +00:00
Akira Hatanaka
7664f05326 Set operation actions for load/store nodes in the Mips backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157866 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 00:04:42 +00:00
Akira Hatanaka
1cd0ec007a Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which 
custom-lower unaligned load and store nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157864 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 00:03:49 +00:00
Akira Hatanaka
b6f1dc2f09 Define Mips specific unaligned load/store nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157863 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 00:03:12 +00:00
Akira Hatanaka
f66b7b1ff6 Expand unaligned i16 loads/stores for the Mips backend. 
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157862 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 00:02:45 +00:00
Akira Hatanaka
28ee4fdf20 Cleanup and factoring of mips16 tablegen classes. Make register classes 
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157730 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-31 02:59:44 +00:00
Justin Holewinski
d2ea0e10cb Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall 
to pass around a struct instead of a large set of individual values.  This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.

NV_CONTRIB

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157479 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-25 16:35:28 +00:00
Akira Hatanaka
92d4aec573 Make the following changes in MipsISelLowering.cpp: 
- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
  before the call node. This will ensure $gp is valid at the entry of the
  called function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156692 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-12 03:19:04 +00:00
Akira Hatanaka
a284acb8a7 Expand 64-bit shifts if target ABI is O32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156457 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-09 00:55:21 +00:00
Eric Christopher
af97f73ca0 Add support for the 'x' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156295 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:25:19 +00:00
Eric Christopher
4adbefebd2 Add support for the 'l' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156294 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:25:15 +00:00
Eric Christopher
1d5a392e2c Add support for the 'c' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156293 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:25:10 +00:00
Eric Christopher
54412a789a Add support for the 'P' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156292 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:25:02 +00:00
Eric Christopher
1ce2034e43 Add support for the 'O' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156285 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:46:48 +00:00
Eric Christopher
60cfc7908e Add support for the 'N' inline asm constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156284 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:46:43 +00:00
Eric Christopher
5ac47bba83 Add support for the 'L' inline asm constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156283 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:46:37 +00:00
Eric Christopher
f49f846eec Add support for the inline asm constraint 'K'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156282 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:46:29 +00:00
Eric Christopher
e5076d484b Support the 'J' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156280 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 03:13:42 +00:00
Eric Christopher
50ab03954e Add support for the 'I' inline asm constraint. Also add tests 
from the previous 2 patches.

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156279 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 03:13:32 +00:00
Eric Christopher
0ed1f764f4 Allow 64 bit integer values in gpu registers if arch and abi are 64 bit. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156278 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 03:13:22 +00:00
Eric Christopher
3ccbd47ecb When using inline asm constraints representing 
non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156277 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 03:13:16 +00:00
Hans Wennborg
fd5abd546e Make ARM and Mips use TargetMachine::getTLSModel() 
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156162 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 09:40:39 +00:00
NAKAMURA Takumi
8959393533 llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build on MSVC. 
Thanks to Andy Gibbs, to report the issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155287 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-21 15:31:45 +00:00
Craig Topper
420761a0f1 Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-20 07:30:17 +00:00
Akira Hatanaka
1cc6333161 Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user, 
otherwise expand FNEG during legalization.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154546 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 22:59:08 +00:00
Akira Hatanaka
c12a6e6b53 Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user. 
Invalid operation is signaled if the operand of these instructions is NaN.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154545 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 22:49:04 +00:00
Akira Hatanaka
056c51e598 Fix bugs in lowering of FCOPYSIGN nodes. 
- FCOPYSIGN nodes that have operands of different types were not handled.
- Different code was generated depending on the endianness of the target.

Additionally, code is added that emits INS and EXT instructions, if they are
supported by target (they are R2 instructions).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154540 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 22:13:04 +00:00
Akira Hatanaka
56ce6b3520 Reapply 154038 without the failing test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154062 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-04 22:16:36 +00:00
Owen Anderson
657a4e774c Revert r154038. It was causing make check failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154054 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-04 21:18:58 +00:00
Akira Hatanaka
e825fb3888 Fix LowerGlobalAddress to produce instructions with the correct relocation 
types for N32 ABI. Add new test case and update existing ones.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154038 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-04 19:02:38 +00:00
Akira Hatanaka
c75ceb7809 Fix LowerJumpTable to produce instructions with the correct relocation 
types for N32 ABI. Test case will be updated after the patch that fixes
TargetLowering::getPICJumpTableRelocBase is checked in.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154036 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-04 18:31:32 +00:00
Akira Hatanaka
86a2733055 Fix LowerConstantPool to produce instructions with the correct relocation 
types for N32 ABI and update test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154034 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-04 18:26:12 +00:00
Akira Hatanaka
03d830e4f9 Fix LowerBlockAddress to produce instructions with the correct relocation 
types for N32 ABI and update test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154031 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-04 18:22:53 +00:00
Akira Hatanaka
21ecc2f4ed Expand FREM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153671 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-29 18:43:11 +00:00
Akira Hatanaka
b4549e1c0e Pass the llvm IR pointer value and offset to the constructor of 
MachinePointerInfo when getStore is called to create a node that stores an
argument passed in register to the stack. Without this change, the post RA 
scheduler will fail to discover the dependencies between the stores
instructions and the instructions that load from a structure passed by value. 

The link to the related discussion is here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-March/048055.html


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153499 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-27 03:13:56 +00:00
Akira Hatanaka
13daee3082 Fix bug in LowerConstantPool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153498 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-27 02:55:31 +00:00
Craig Topper
79aa3417eb Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-17 18:46:09 +00:00
Craig Topper
c5eaae4e9b Convert more static tables of registers used by calling convention to uint16_t to reduce space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-11 07:57:25 +00:00
Akira Hatanaka
d229b7b8f4 Do not custom lower i64 nodes if i64 is not a legal type. Move lines that set 
operation action of nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152452 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-10 00:03:50 +00:00
Akira Hatanaka
0a40c2353c Lower SETCC nodes during legalization. Previously, it was lowered in DAG combine pass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152450 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-09 23:46:03 +00:00
Akira Hatanaka
ee8c3b03fb Invoke setTargetDAGCombine for SELECT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152290 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-08 03:26:37 +00:00
Akira Hatanaka
e2bdf7fc93 Swap the operands of a select node if the false (the second) operand is 0. 
For example, this pattern 
(select (setcc lhs, rhs, cc), true, 0)
is transformed to this one:
(select (setcc lhs, rhs, inverse(cc)), 0, true)

This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to
replace 0 with $zero.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152285 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-08 02:14:24 +00:00
Akira Hatanaka
5fdf50065d Set minimum function alignment to 3 if target is Mips64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152282 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-08 01:59:33 +00:00
Akira Hatanaka
b2930b92d3 Changes for migrating to using register mask operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151847 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-01 22:27:29 +00:00
Akira Hatanaka
dfa27aea12 Fix bugs which were introduced when support for base+index floating point loads 
and stores was added.

- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
  floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151843 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-03-01 22:12:30 +00:00
Evan Cheng
4bfcd4acbc Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-28 18:51:51 +00:00