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Author SHA1 Message Date
Jakob Stoklund Olesen
eda0fe8d58 Use InterferenceCache in RegAllocGreedy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128765 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 06:03:38 +00:00
Jakob Stoklund Olesen
5907d86365 Add an InterferenceCache class for caching per-block interference ranges. 
When the greedy register allocator is splitting multiple global live ranges, it
tends to look at the same interference data many times. The InterferenceCache
class caches queries for unaltered LiveIntervalUnions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128764 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 06:03:35 +00:00
Jakob Stoklund Olesen
a122eaaee2 Use basic block numbers as indexes when mapping slot index ranges. 
This is more compact and faster than using DenseMap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128763 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 06:03:31 +00:00
Cameron Zwarich
4071a71112 Do some peephole optimizations to remove pointless VMOVs from Neon to integer 
registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128759 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 02:40:43 +00:00
Cameron Zwarich
ed3caf9086 Add a RemoveFromWorklist method to DCI. This is needed to do some complicated 
transformations in target-specific DAG combines without causing DAGCombiner to
delete the same node twice. If you know of a better way to avoid this (see my
next patch for an example), please let me know.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128758 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 02:40:26 +00:00
Johnny Chen
04187ecd57 Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset; 
instead of the second operand in addrmode_imm12.

rdar://problem/9225289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128757 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 02:24:54 +00:00
Akira Hatanaka
ad8ffad60a Undo changes mistakenly made in revision 128750. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128751 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 00:26:12 +00:00
Akira Hatanaka
dc1652fd31 Insert space before ';' to prevent warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128750 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-02 00:15:58 +00:00
Johnny Chen
103bf951a4 Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000. 
rdar://problem/9224276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128749 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 23:30:25 +00:00
Johnny Chen
6da3fe68c6 MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE. 
rdar://problem/9224120


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128748 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 23:15:50 +00:00
Johnny Chen
857b1939da Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that 
all the instruction have:

    let Inst{31-27} = 0b1110; // non-predicated

Before, the ARM decoder was confusing:

> 0x40 0xf3 0xb8 0x80

as:

Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcs	pc, r8, r0, asr #6

since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.

Now, the AR decoder behaves correctly:

> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt

Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcshi	pc, r8, r0, asr #6
> 

rdar://problem/9223094


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 22:32:51 +00:00
Benjamin Kramer
406a650237 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128745 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 22:29:18 +00:00
Benjamin Kramer
5337fabdc4 Tweaks to the icmp+sext-to-shifts optimization to address Frits' comments: 
- Localize the check if an icmp has one use to a place where we know we're
  introducing something that's likely more expensive than a sext from i1.
- Add an assert to make sure a case that would lead to a miscompilation is
  folded away earlier.
- Fix a typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128744 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 22:22:11 +00:00
Evan Cheng
0539c159fb Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128743 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 22:09:28 +00:00
Akira Hatanaka
ad8180a0b8 Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128742 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 21:56:02 +00:00
Akira Hatanaka
e2e436a6bc Simplifies logic for printing target flags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128741 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 21:41:06 +00:00
Owen Anderson
1721324d97 When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 21:07:39 +00:00
Jim Grosbach
9a3507f091 LDRD/STRD instructions should print both Rt and Rt2 in the asm string. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128736 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 20:26:57 +00:00
Johnny Chen
ec30f6f5e5 Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction 
as invalid.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128734 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 20:21:38 +00:00
Benjamin Kramer
ce1498bdbe Fix build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128733 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 20:15:16 +00:00
Benjamin Kramer
0baa94a13b InstCombine: Turn icmp + sext into bitwise/integer ops when the input has only one unknown bit. 
int test1(unsigned x) { return (x&8) ? 0 : -1; }
int test3(unsigned x) { return (x&8) ? -1 : 0; }

before (x86_64):
_test1:
	andl	$8, %edi
	cmpl	$1, %edi
	sbbl	%eax, %eax
	ret
_test3:
	andl	$8, %edi
	cmpl	$1, %edi
	sbbl	%eax, %eax
	notl	%eax
	ret

after:
_test1:
	shrl	$3, %edi
	andl	$1, %edi
	leal	-1(%rdi), %eax
	ret
_test3:
	shll	$28, %edi
	movl	%edi, %eax
	sarl	$31, %eax
	ret

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128732 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 20:09:10 +00:00
Benjamin Kramer
0a30c42008 InstCombine: Move (sext icmp) transforms into their own method. No intended functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128731 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 20:09:03 +00:00
Evan Cheng
c249e48558 Add comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128730 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 19:57:01 +00:00
Evan Cheng
8380c034b6 Assign node order numbers to results of call instruction lowering. This should improve src line debug info when sdisel is used. rdar://9199118 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128728 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 19:42:22 +00:00
Akira Hatanaka
a4485c4964 Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128724 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 18:57:38 +00:00
Johnny Chen
5307da994a Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). 
rdar://problem/9219356


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128722 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 18:26:38 +00:00
Akira Hatanaka
20ada98de8 Add code for analyzing FP branches. Clean up branch Analysis functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128718 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 17:39:08 +00:00
Benjamin Kramer
0e3ee43ea0 Initialize HasVMLxForwarding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 09:20:31 +00:00
Jay Foad
8891ed7ac9 Various Instructions' resizeOperands() methods are only used to grow the 
list of operands. Simplify and rename them accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128708 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 08:00:58 +00:00
Duncan Sands
607946533d While testing dragonegg I noticed that isCastable and getCastOpcode 
had gotten out of sync: isCastable didn't think it was possible to
cast the x86_mmx type to anything, while it did think it possible
to cast an i64 to x86_mmx.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128705 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 03:34:54 +00:00
Evan Cheng
8e23e815ad Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs. 
rdar://8911343


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 00:42:02 +00:00
Matt Beaumont-Gay
e3662cca5d Remove unused variables 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128692 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-01 00:06:01 +00:00
Bruno Cardoso Lopes
ae0855401b Apply again changes to support ARM memory asm parsing. I removed 
all LDR/STR changes and left them to a future patch. Passing all
checks now.

- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 23:26:08 +00:00
Jakob Stoklund Olesen
842759662b The basic register allocator must also use the inline spiller. 
It is using a trivial rewriter that doesn't know how to insert spill code
requested by the standard spiller.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128688 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 23:02:17 +00:00
Jakob Stoklund Olesen
1db952d0c6 Provide a legal pointer register class when targeting thumb1. 
The LocalStackSlotAllocation pass was creating illegal registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128687 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 23:02:15 +00:00
Nadav Rotem
0ff8a4fa35 Instcombile optimization: extractelement(cast) -> cast(extractelement) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128683 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 22:57:29 +00:00
Benjamin Kramer
7ebdc37d2b InstCombine: APFloat can't perform arithmetic on PPC double doubles, don't even try. 
Thanks Eli!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128676 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 21:35:49 +00:00
Evan Cheng
463d358f1d Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier 
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128665 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 19:38:48 +00:00
Johnny Chen
a52d7da1d8 Fix single word and unsigned byte data transfer instruction encodings so that 
Inst{4} = 0.

rdar://problem/9213022


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128662 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 19:28:35 +00:00
Akira Hatanaka
1d6b38d9d3 Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128650 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 18:26:17 +00:00
Jakob Stoklund Olesen
280ea1a746 Don't completely eliminate identity copies that also modify super register liveness. 
Turn them into noop KILL instructions instead. This lets the scavenger know when
super-registers are killed and defined.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128645 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 17:55:25 +00:00
Johnny Chen
8901e6ff3d Add BLXi to the instruction table for disassembly purpose. 
A8.6.23 BLX (immediate)

rdar://problem/9212921


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128644 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 17:53:50 +00:00
Jakob Stoklund Olesen
02ae9f2f27 Allow kill flags on two-address instructions. They are harmless. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128643 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 17:52:41 +00:00
Jakob Stoklund Olesen
8e53aca51a Mark all uses as <undef> when joining a copy. 
This way, shrinkToUses() will ignore the instruction that is about to be
deleted, and we avoid leaving invalid live ranges that SplitKit doesn't like.

Fix a misunderstanding in MachineVerifier about <def,undef> operands. The
<undef> flag is valid on def operands where it has the same meaning as <undef>
on a use operand. It only applies to sub-register defines which also read the
full register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128642 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 17:23:25 +00:00
Devang Patel
e62dfcf4b3 Remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128639 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 16:53:49 +00:00
Bruno Cardoso Lopes
b41aaab5a1 Revert r128632 again, until I figure out what break the tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 15:54:36 +00:00
Jakob Stoklund Olesen
314a3ef502 Fix bug found by valgrind. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128634 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 15:14:11 +00:00
Richard Osborne
e8f3533323 Add XCore intrinsics for initializing / starting / synchronizing threads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128633 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 15:13:13 +00:00
Bruno Cardoso Lopes
bcd3a9cd84 Reapply r128585 without generating a lib depedency cycle. An updated log: 
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
  addrmode2.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128632 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 14:52:28 +00:00
NAKAMURA Takumi
dc5198bac7 lib/CodeGen/LiveIntervalAnalysis.cpp: [PR9590] Don't use std::pow(float,float) here. 
We don't expect the real "powf()" on some hosts (and powf() would be available on other hosts).
For consistency, std::pow(double,double) may be called instead.
Or, precision issue might attack us, to see unstable regalloc and stack coloring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128629 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-31 12:11:33 +00:00