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Author SHA1 Message Date
Evan Cheng 7e2fe9150f Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 06:47:08 +00:00
Evan Cheng 9c3e8e28bd Disable most of the ARM vfp / NEON MC tests. These are too fragile to be useful. 
I'll work with Jim, Owen, and Bill on an alternative testing strategy until
the assembly parser is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117530 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 06:46:17 +00:00
Evan Cheng 9e08ee5d16 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 02:00:25 +00:00
Evan Cheng 0104d9de04 - Assign load / store with shifter op address modes the right itinerary classes. 
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 01:49:06 +00:00
Evan Cheng 7c88cdcc3b Fix a major bug in operand latency computation. The use index must be adjusted 
by the number of defs first for it to match the instruction itinerary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117518 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 01:46:29 +00:00
Evan Cheng f40deed62f Shifter ops are not always free. Do not fold them (especially to form 
complex load / store addressing mode) when they have higher cost and
when they have more than one use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117509 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 23:41:30 +00:00
Evan Cheng de5fa932b9 Putting r117193 back except for the compile time cost. Rather than assuming fallthroughs uses all registers, just gather the union of all successor liveins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117506 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 23:17:17 +00:00
Evan Cheng c8141dfc7f Use instruction itinerary to determine what instructions are 'cheap'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 02:08:50 +00:00
Evan Cheng 0e9996ca94 NEON vmov's are in Neon domain. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117347 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 02:03:05 +00:00
Evan Cheng 38fd9f2a2d Neuter r117193 as it causes significant post-ra scheduler compile time regression. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117329 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 23:56:21 +00:00
Evan Cheng 5c2d428f43 Enable ARM fastcc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-23 02:19:37 +00:00
Evan Cheng ec6906ba47 Properly model the latency of register defs which are 1) function returns or 
2) live-outs.

Previously the post-RA schedulers completely ignore these dependencies since
returns, branches, etc. are all scheduling barriers. This patch model the
latencies between instructions being scheduled and the barriers. It also
handle calls by marking their register uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117193 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-23 02:10:46 +00:00
Evan Cheng dd9dd6f857 Latency between CPSR def and branch is zero. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117192 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-23 02:04:38 +00:00
Evan Cheng c8f46c45a0 Unbreak build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117155 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 21:49:09 +00:00
Evan Cheng b179b46cc5 Transfer implicit ops when forming load multiple and return instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117151 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 21:29:58 +00:00
Evan Cheng 1f8b40d51c Silence compiler warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117128 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 18:57:05 +00:00
Evan Cheng 76f920d316 Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117119 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 18:23:05 +00:00
Evan Cheng d6865de2d2 Add missing scheduling itineraries for transfers between core registers and VFP registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116983 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 01:12:00 +00:00
Evan Cheng 134982daa9 More accurate estimate / tracking of register pressure. 
- Initial register pressure in the loop should be all the live defs into the
  loop. Not just those from loop preheader which is often empty.
- When an instruction is hoisted, update register pressure from loop preheader
  to the original BB.
- Treat only use of a virtual register as kill since the code is still SSA.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116956 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-20 22:03:58 +00:00
Evan Cheng 2312842de0 Re-enable register pressure aware machine licm with fixes. Hoist() may have 
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116845 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-19 18:58:51 +00:00
Evan Cheng 11e8b74a7a - Add a hook for target to determine whether an instruction def is 
"long latency" enough to hoist even if it may increase spilling. Reloading
  a value from spill slot is often cheaper than performing an expensive
  computation in the loop. For X86, that means machine LICM will hoist
  SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
  instructions.
- Enable register pressure aware machine LICM by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-19 00:55:07 +00:00
Evan Cheng 03a9fdf2e7 More machine LICM work. It now tracks register pressure for path from preheader to current BB and use the information determine whether hoisting is worthwhile. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116654 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-16 02:20:26 +00:00
Evan Cheng 0e673919f0 Register pressure and instruction latency aware machine LICM. Work in progress. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116465 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 01:16:09 +00:00
Evan Cheng 14ce175216 Limit load / store issues (at least until we have a true multi-issue aware scheduler). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116389 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 01:54:21 +00:00
Evan Cheng 3f490f3469 Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116368 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:19:28 +00:00
Evan Cheng 08cec1ef27 More ARM scheduling itinerary fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116266 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:41:41 +00:00
Evan Cheng 60ff87914f Proper VST scheduling itineraries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116251 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 22:03:18 +00:00
Evan Cheng 10dc63feeb Add VLD4 scheduling itineraries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116143 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 04:07:58 +00:00
Evan Cheng 84f69e8436 Finish vld3 and vld4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116140 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 01:45:34 +00:00
Evan Cheng 40bb6836f6 Complete vld2 instruction itineries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116136 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 01:26:12 +00:00
Evan Cheng 8ae6ffacdd Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116135 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 01:15:04 +00:00
Evan Cheng d2ca813549 Correct some load / store instruction itinerary mistakes: 
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-09 01:03:04 +00:00
Evan Cheng d82de8341c Avoid compiler warning: comparison between signed and unsigned integer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116119 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 23:01:57 +00:00
Evan Cheng e95f3195b8 Don't waste time unfolding simple loads. The unfolded copy won't be hoisted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116081 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 18:59:19 +00:00
Evan Cheng 1aca5bc135 Fix operand latency computation in cases where the definition operand is 
implicit. e.g.
%D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def>                                                                                                                                                                              
%Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ...

The real definition indices are 0,1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116080 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 18:42:25 +00:00
Evan Cheng 344d9db970 Code refactoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116002 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 23:12:15 +00:00
Evan Cheng a98111cf15 Correctly check if a path is a directory. Fix by Brian Korver. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115991 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 22:05:57 +00:00
Evan Cheng 835580fc3a Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115977 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 20:50:20 +00:00
Evan Cheng 5a50ceeaea Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115898 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-07 01:50:48 +00:00
Evan Cheng a0792de66c - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This 
allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 06:27:31 +00:00
Evan Cheng 2a135ae530 This DAG combine BRCOND transformation can look pass truncate of the operand: 
//   %a = ...                                                                                                                                                                                  
    //   %b = and i32 %a, 2                                                                                                                                                                        
    //   %c = srl i32 %b, 1                                                                                                                                                                        
    //   brcond i32 %c ...                                                                                                                                                                         
    //                                                                                                                                                                                             
    // into                                                                                                                                                                                        
    //                                                                                                                                                                                             
    //   %a = ...                                                                                                                                                                                  
    //   %b = and i32 %a, 2                                                                                                                                                                        
    //   %c = setcc eq %b, 0                                                                                                                                                                       
    //   brcond %c ...

Make sure it restores local variable N1, which corresponds to the condition operand if it fails to match.

This apparently breaks TCE but since that backend isn't in the tree I don't have a test for it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115571 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-04 22:41:01 +00:00
Evan Cheng ec45f60cab Major changes to Cortex-A9 itinerary. 
1. Model dual issues as two FUs.
2. Model the pipelines correctly: two symmetric ALUs, the multiplier is a
   dependent pipeline on ALU0.
The changes do not have much impact on codegen right now. But I plan to make
pre-RA scheduler multi-issue aware which should take good advantage of the
changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115457 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-03 02:03:59 +00:00
Evan Cheng 055028215d Fix r115332: correctly model AGU / NEON mux. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115365 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 22:52:29 +00:00
Evan Cheng ef0ccad725 Fix scheduling infor for vmovn and vshrn which I broke accidentially. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115354 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 21:48:06 +00:00
Evan Cheng df9da6a033 Add operand cycles for vldr / vstr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115353 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 21:40:30 +00:00
Evan Cheng cae6a12a99 NEON scheduling info fix. vmov reg, reg are single cycle instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115344 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 20:50:58 +00:00
Evan Cheng 7c3423f413 Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP issue are multiplexed. Model it correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115332 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 19:41:46 +00:00
Evan Cheng a56927e3ff Comments about operand cycles and pipeline forwarding pathes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115214 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 22:01:50 +00:00
Evan Cheng 0e55fd61ae ARM instruction itinerary fixes: 
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115121 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 01:08:25 +00:00
Evan Cheng 3881cb7a5d Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP 
pipeline forwarding path.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115098 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 22:42:35 +00:00
Evan Cheng 5d42c567c9 Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115010 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 00:49:25 +00:00
Evan Cheng 7e1bf305cf Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115008 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 00:27:46 +00:00
Evan Cheng 63d66eed16 Add support to model pipeline bypass / forwarding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-28 23:50:49 +00:00
Evan Cheng 5981fc6788 Fix IIC_iEXTAr itinerary class of Cortex-A9. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114784 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-25 01:09:28 +00:00
Evan Cheng 27fdcd1c95 Remove a unused instruction itinerary class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114782 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-25 01:06:02 +00:00
Evan Cheng 576a3968a2 Fix zero and sign extension instructions scheduling itineraries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114780 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-25 00:49:35 +00:00
Evan Cheng bd30ce4311 More pseudo instruction scheduling itinerary fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114768 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-24 22:41:41 +00:00
Evan Cheng 5be3922321 Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114766 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-24 22:03:46 +00:00
Evan Cheng fff606d7b2 Enable code placement optimization pass for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-24 19:07:23 +00:00
Evan Cheng de0e11c8f3 Fix a potential null dereference bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114723 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-24 05:18:35 +00:00
Evan Cheng 676e258366 Fix r114632. Return if the only terminator is an unconditional branch after the redundant ones are deleted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114688 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 19:42:03 +00:00
Evan Cheng 8c1f4329e2 Revert 114634 for now since buildbot claim it broke Clang self-hosting. I doubt it but it's possible it's exposing another bug somewhere. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114681 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 18:32:19 +00:00
Evan Cheng b8db1981b8 Follow up to r114630. Do not optimize away unconditional branch following a conditional one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114634 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 07:18:35 +00:00
Evan Cheng dd3a41a6b3 Disable codegen prepare critical edge splitting. Machine instruction passes now 
break critical edges on demand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114633 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 06:55:34 +00:00
Evan Cheng 108c872466 If there are multiple unconditional branches terminating a block, eliminate all 
but the first one. Those will never be executed. There was logic to do this
but it was faulty.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114632 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 06:54:40 +00:00
Evan Cheng b0cdf8a446 Don't sink insert_subreg, subreg_to_reg, reg_sequence. They are meant to be 
close to their sources to facilitate coalescing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114631 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 06:53:00 +00:00
Evan Cheng 266a99d161 SDISel should not optimize a unconditional branch following a conditional branch 
when the unconditional branch destination is the fallthrough block. The
canonicalization makes it easier to allow optimizations on DAGs to invert
conditional branches. The branch folding pass (and AnalyzeBranch) will clean up
the unnecessary unconditional branches later.

This is one of the patches leading up to disabling codegen prepare critical edge
splitting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114630 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 06:51:55 +00:00
Evan Cheng 691e64a54c OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114506 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-21 23:49:07 +00:00
Evan Cheng 44be1a8d66 Enable machine sinking critical edge splitting. e.g. 
define double @foo(double %x, double %y, i1 %c) nounwind {
  %a = fdiv double %x, 3.2
  %z = select i1 %c, double %a, double %y
  ret double %z
}

Was:
_foo:
        divsd   LCPI0_0(%rip), %xmm0
        testb   $1, %dil
        jne     LBB0_2
        movaps  %xmm1, %xmm0
LBB0_2:
        ret

Now:
_foo:
        testb   $1, %dil
        je      LBB0_2
        divsd   LCPI0_0(%rip), %xmm0
        ret
LBB0_2:
        movaps  %xmm1, %xmm0
        ret

This avoids the divsd when early exit is taken.
rdar://8454886


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114372 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-20 22:52:00 +00:00
Evan Cheng 7af6dc47a5 Avoid splitting critical edge twice for a set of PHI uses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114338 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-20 19:12:55 +00:00
Evan Cheng 2399786b27 Fix code that break critical edges for PHI uses. Watch out for multiple PHIs in different blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114270 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-18 06:42:17 +00:00
Evan Cheng 6edb0eac87 Teach machine sink to 
1) Do forward copy propagation. This makes it easier to estimate the cost of the
   instruction being sunk.
2) Break critical edges on demand, including cases where the value is used by
   PHI nodes.
Critical edge splitting is not yet enabled by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114227 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 22:28:18 +00:00
Evan Cheng c2b768f09e Machine CSE was forgetting to clear some data structures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114222 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 21:59:42 +00:00
Evan Cheng f437f73348 Fix a potential bug that can cause miscomparison with and without debug info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114220 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 21:56:26 +00:00
Evan Cheng 3dc0bb3afd Fix test so it passes on non-Darwin hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113577 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-10 06:20:01 +00:00
Evan Cheng 3ef1c8759a Teach if-converter to be more careful with predicating instructions that would 
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-10 01:29:16 +00:00
Evan Cheng 5f54ce3473 For each instruction itinerary class, specify the number of micro-ops each 
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-09 18:18:55 +00:00
Evan Cheng 7602acbf3b Fix LDM_RET schedule itinery. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113435 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-08 22:57:08 +00:00
Evan Cheng dc0b06c815 Remove a dead comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113259 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 20:01:10 +00:00
Evan Cheng f942c13af8 Update debug logs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111575 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 23:33:02 +00:00
Evan Cheng 19708923be Properly update MachineDominators when splitting critical edge. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111574 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 23:32:47 +00:00
Evan Cheng e5e7946018 It's possible to sink a def if its local uses are PHI's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111537 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 18:33:29 +00:00
Evan Cheng c546c75459 Remove disabled assertion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111531 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 17:33:48 +00:00
Evan Cheng 4dc301a7c5 Teach machine-sink to break critical edges when appropriate. Work in progress. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111530 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-19 17:33:11 +00:00
Evan Cheng c3439ad63f If any def of a machine-sink candidate has local uses, it's obviously not safe to sink it to a successor block. This bug has been hidden because a later check for critical-edge disable these illegal optimizations. This patch should significantly reduce the amount of time spent on checking dominator information for obviously unsafe sinking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111450 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-18 23:09:25 +00:00
Evan Cheng b9072fdaad Add nounwind. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111312 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 22:35:20 +00:00
Evan Cheng 148341cc9b PHI elimination shouldn't require machineloopinfo since it's used at -O0. Move the requirement to LiveIntervalAnalysis instead. Note this does not change the number of times machineloopinfo is computed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111285 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 21:00:37 +00:00
Evan Cheng 6542416560 Machine CSE preserves CFG. Pass manager was freeing machineloopinfo after machine cse before. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111281 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 20:57:42 +00:00
Evan Cheng e008384508 Move the decision logic whether it's a good idea to split a critical edge to clients. Also fixed an erroneous check. An edge is only a back edge when the from and to blocks are in the same loop. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111256 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 17:43:50 +00:00
Evan Cheng 087fbeb7d1 Fix debug message. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111250 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 17:15:14 +00:00
Evan Cheng e1bcb440dc Add an option to disable codegen prepare critical edge splitting. In theory, PHI elimination is already doing all (most?) of the splitting needed. But machine-licm and machine-sink seem to miss some important optimizations when splitting is disabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111224 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 01:34:49 +00:00
Evan Cheng 97b9b97853 PHI elimination should not break back edge. It can cause some significant code placement issues. rdar://8263994 
good:
LBB0_2:
  mov     r2, r0
  . . .
  mov     r1, r2
  bne     LBB0_2

bad:
LBB0_2:
  mov     r2, r0
  . . .
@ BB#3:
  mov     r1, r2
  b       LBB0_2


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111221 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-17 01:20:36 +00:00
Evan Cheng 719510a178 Make sure ARM constant island pass does not break up an IT block. If the split point is in the middle of an IT block, it should move it up to just above the IT instruction. rdar://8302637 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110947 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-12 20:30:05 +00:00
Evan Cheng e1f0859789 Fix test and re-enable it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110829 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 17:25:51 +00:00
Evan Cheng 7b4d31176e Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 07:17:46 +00:00
Evan Cheng 8d62e713ea ArchV7M implies HW division instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110797 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 07:00:16 +00:00
Evan Cheng cb5ce6e62b ArchV6T2, V7A, and V7M implies Thumb2; Archv7A implies NEON. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110796 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:57:53 +00:00
Evan Cheng d6b4632256 Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:51:54 +00:00
Evan Cheng ee34987fd5 Really control isel of barrier instructions with cpu feature. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110787 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:36:31 +00:00
Evan Cheng c7569ed4e4 Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit 
instructions: dmb, dsb, isb, msr, and mrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110786 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-11 06:30:38 +00:00