6502/llvm-6502
1
0 Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2026-04-27 04:18:42 +00:00
Code Issues Projects Releases Wiki Activity
66,364 Commits 39 Branches 0 Tags
f22b74608ede59dabc55fab66f2142f369f9dbfb
Commit Graph
100 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Jim Grosbach 7e3383c007 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 23:12:14 +00:00
Jim Grosbach 6b15639e26 Trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117496 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 21:39:08 +00:00
Jim Grosbach ccf72caa92 JIT imm12 encoding for constant pool entry references. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117483 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 20:39:40 +00:00
Jim Grosbach f31430f6ec ARM JIT fix for LDRi12 and company. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117478 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 19:55:59 +00:00
Jim Grosbach 093177d5cd The new LDR* instruction patterns should handle the necessary encoding of 
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117461 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 17:52:51 +00:00
Jim Grosbach 063efbf569 The immediate operands of an LDRi12 instruction doesn't need the addrmode2 
encoding tricks. Handle the 'imm doesn't fit in the insn' case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117454 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 16:50:31 +00:00
Jim Grosbach 0ed257c036 Formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117453 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 16:30:18 +00:00
Jim Grosbach 77aee8e22c LDRi12 machine instructions handle negative offset operands normally (simple 
integer values), not with the addrmode2 encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117429 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 01:19:41 +00:00
Jim Grosbach f85dd04bfa One more spot where the new arm mode LDR instruction representation 
doesn't need the additional addrmode2 register operand. Missed it the first
time around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117421 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 00:38:16 +00:00
Jim Grosbach c1d30212e9 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117419 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 00:19:44 +00:00
Jim Grosbach 28e3fe961f Since I parameterized this bit, I should probably actually use said parameter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117418 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 23:58:04 +00:00
Jim Grosbach 3e55612472 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 22:37:02 +00:00
Jim Grosbach 8ac98cb665 FileCheck'ize 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117401 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 21:26:47 +00:00
Jim Grosbach 0eb7d06ab1 Grammar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117388 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 19:34:41 +00:00
Jim Grosbach c3baf62800 Nuke extraneous comment. It's applicable elsewhere, but not in this func. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117387 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 19:22:23 +00:00
Jim Grosbach 458f2dc5d1 imm12 operands aren't Thumb2 only, so rename the printer helper function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117291 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-25 20:00:01 +00:00
Jim Grosbach a9a968d1ef Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117188 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 23:48:29 +00:00
Jim Grosbach 48c9f2081d Add a CMP test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117187 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 23:48:01 +00:00
Jim Grosbach b2331553f8 tidy up 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117185 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 23:46:04 +00:00
Jim Grosbach 432a8142ef tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117166 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 22:15:48 +00:00
Jim Grosbach f8da5f5dfa ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117165 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 22:12:16 +00:00
Jim Grosbach 871bf8752f Remove duplicate test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117158 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 22:04:28 +00:00
Jim Grosbach d0ad5d52b8 tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117157 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 22:01:56 +00:00
Jim Grosbach 487119a08c FileCheck-ize a few tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117156 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 21:55:03 +00:00
Jim Grosbach 385e136dce Add the encoding information for the rest of the ARM mode multiply instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117133 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 19:15:30 +00:00
Jim Grosbach 3870b750e6 More ARM multiply instuction binary encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117121 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 18:35:16 +00:00
Jim Grosbach 929a7056d8 Parameterize a bit of ARM encoding information, simplifying some instruction 
definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117114 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 17:42:06 +00:00
Jim Grosbach 9463d0e400 More ARM multiply instruction encoding information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117108 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-22 17:16:17 +00:00
Jim Grosbach f50af8b5b8 ARM binary encoding for some of the multiply instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117080 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 22:52:30 +00:00
Jim Grosbach 3686046a2c ARM binary encodings for MVN variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117076 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 22:19:32 +00:00
Jim Grosbach fe40f9551c Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117073 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 22:04:05 +00:00
Jim Grosbach 3fea19105d ARM Binary encoding information for BFC/BFI instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117072 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 22:03:21 +00:00
Jim Grosbach 3ab5658a12 trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117050 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-21 19:38:40 +00:00
Jim Grosbach b8e67fc92b Fix backwards conditional. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116897 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-20 01:10:01 +00:00
Jim Grosbach 8b95c3ebfb Add dynamic realignment when rematerializing the base register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116886 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-20 00:02:50 +00:00
Jim Grosbach f6d7df6f21 Nuke a commented out bit that got missed a while back. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116883 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-19 23:48:47 +00:00
Jim Grosbach df7ec2083f Spelling typo fix. s/incput/input/. Thanks, Bob! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116880 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-19 23:39:23 +00:00
Jim Grosbach e4ad387a5a Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any 
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116879 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-19 23:27:08 +00:00
Jim Grosbach 8155ea4c3a Update comments to remove obsolete references. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116863 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-19 21:34:47 +00:00
Jim Grosbach 70987fbc60 ARM encoding information for [SU]SAT* instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116768 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 23:35:38 +00:00
Jim Grosbach 5c57639c28 For Thumb2, try to use frame pointer references for stack slots even when a 
base register is available. rdar://8525298

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116729 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 18:39:46 +00:00
Jim Grosbach 0f0127f4a6 ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediate 
offset for stack references. Make sure we take that into account when
deciding whether to reserver an emergency spill slot for the register
scavenger. rdar://8559625

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116714 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 16:48:59 +00:00
Jim Grosbach e038a206df Grammar tweak. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116712 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 16:38:50 +00:00
Jim Grosbach c0c7c2b606 Trivial grammar tweak. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116710 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-18 16:29:26 +00:00
Jim Grosbach 5ad01c7728 Encoding information for the various ARM saturating add/sub instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116612 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 19:49:46 +00:00
Jim Grosbach 84760885e1 ARM binary encoding information for RSB and RSC instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116604 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 18:42:41 +00:00
Jim Grosbach fd52906478 Don't mark argument value stores as immutable, as otherwise the post-RA 
scheduler may reorder loads from them before the stores and other such
badness. PR8347. Patch by David Meyer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116602 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 18:34:47 +00:00
Jim Grosbach 6bdc8ae291 When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomes 
an explicit def. Make sure to capture that properly. rdar://8556556

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116591 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 17:35:17 +00:00
Jim Grosbach 8abe32af38 ARM mode encoding information for UBFX and SBFX instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116588 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 17:15:16 +00:00
Jim Grosbach 197a8df640 Encoding info for extension instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116560 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 02:29:58 +00:00
Jim Grosbach cbc549e81c Grammar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116557 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-15 01:44:59 +00:00
Jim Grosbach 53e7dcbd47 Simplify test file a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116540 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 23:32:44 +00:00
Jim Grosbach 8faff9c759 Add testcase for RRX and ASRS (which effectively tests MOVs, since those 
are just forms of that instruction).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116538 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 23:29:18 +00:00
Jim Grosbach 58456c0b04 Add missing Rd encoding for MOVs instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116537 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 23:28:31 +00:00
Jim Grosbach 7032f922b1 Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos 
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116534 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 22:57:13 +00:00
Jim Grosbach 792e9796b3 Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx' 
pseudonym.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116512 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 20:43:44 +00:00
Jim Grosbach 1de588df69 MOVi16 and MOVT ARM mode encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116498 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 18:54:27 +00:00
Jim Grosbach 2d294f564b Simplify encoding information and add 'dst' operand info for TAILJMP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116488 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 17:24:28 +00:00
Jim Grosbach bd38acfa6f Regenerate. No functional change, just cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116459 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 00:15:18 +00:00
Jim Grosbach 41045ba731 Teach PerfectShuffle to not generate files with embedded tab characters. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116458 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-14 00:12:49 +00:00
Jim Grosbach 55561d1882 Detabify and clean up 80 column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116454 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 23:47:11 +00:00
Jim Grosbach 95369599c6 A few 80 column fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116451 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 23:34:31 +00:00
Jim Grosbach 3a37866e53 trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116450 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 23:12:26 +00:00
Jim Grosbach b4b07b93ea Add a FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116449 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 22:55:33 +00:00
Jim Grosbach 06ef444e5c Add operand encoding bits for SMC and SVC in ARM mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116447 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 22:38:23 +00:00
Jim Grosbach 832859d062 More encoding cleanup. Also add register Rd operands for indirect branches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116444 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 22:09:34 +00:00
Jim Grosbach a7dbc1ead7 Simplify some ARM encoding information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116440 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:48:54 +00:00
Jim Grosbach 6c354fd3f5 Add a FIXME. The ADR instruction is a bit odd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116437 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:32:30 +00:00
Jim Grosbach b3af5de2d9 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern 
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 21:00:04 +00:00
Jim Grosbach 596307e133 Add a FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116428 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 20:38:04 +00:00
Jim Grosbach fa7d2cb680 Make a few more bits of some simple instructions explicit. nop, yield, wfe, 
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116427 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 20:30:55 +00:00
Jim Grosbach b35ad41fef Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 19:56:10 +00:00
Jim Grosbach e822f94509 Fix encoding for compares. No Rd register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116414 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 18:05:25 +00:00
Jim Grosbach 24989ecc70 Add ARM mode operand encoding information for ADDE/SUBE instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116412 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 18:00:52 +00:00
Jim Grosbach 89c898f8af Add ARM encoding information for comparisons, forced-cc-out arithmetics, and 
arithmetic-with-carry-in instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116384 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-13 00:50:27 +00:00
Jim Grosbach ef324d7044 Add the rest of the ARM so_reg encoding options (register shifted register) 
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:53:58 +00:00
Jim Grosbach 2a6a93d542 Move the ARM so_imm encoding into a custom operand encoder and remove the 
explicit handling of the instructions referencing it from the MC code
emitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116367 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:18:08 +00:00
Jim Grosbach c14b80f6d3 Be nitpicky and line up the comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116365 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:14:03 +00:00
Jim Grosbach 08bd54987f Add custom encoder for the 's' bit denoting whether an ARM arithmetic 
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 23:00:24 +00:00
Jim Grosbach 5013f7469e Allow targets to optionally specify custom binary encoder functions for 
operand values. This is useful for operands which require additional trickery
to encode into the instruction. For example, the ARM shifted immediate and
shifted register operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116353 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 22:21:57 +00:00
Jim Grosbach 499e886fe6 Encoding for ARM-mode VADD.F32 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116338 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 21:22:40 +00:00
Jim Grosbach 82635f080c Comment grammar tweakage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116322 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:11:41 +00:00
Jim Grosbach f59818b81a Add MOVi ARM encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116321 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 18:09:12 +00:00
Jim Grosbach 8e157302f4 Nuke unused wrapper function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:53:25 +00:00
Jim Grosbach 0de6ab3c43 Add encoding information for the remainder of the generic arithmetic 
ARM instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-12 17:11:26 +00:00
Jim Grosbach 42fac8ee3b MC machine encoding for simple aritmetic instructions that use a shifted 
register operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 23:16:21 +00:00
Jim Grosbach a1e2194f03 The assert() should reference to machine instr operand number, too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116243 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 21:41:31 +00:00
Jim Grosbach 1a7233f9d0 Make sure to use the machine instruction operand number. It doesn't always 
map one-to-one with the CodeGenInstruction operand number.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116238 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 21:31:22 +00:00
Jim Grosbach c4bd6fbf4b trailing whitespace cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116215 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 19:38:01 +00:00
Jim Grosbach 62547267f0 More binary encoding stuff, taking advantage of the new "by name" operand 
matching in tblgen to do the predicate operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116213 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 18:51:51 +00:00
Jim Grosbach 01855071e2 When figuring out which operands match which encoding fields in an instruction, 
try to match them by name first. If there is no by-name match, fall back to
assuming they are in order (this was the previous behavior).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116211 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-11 18:25:51 +00:00
Jim Grosbach 56ac907c57 Implement a few more binary encoding bits. Still very early stage proof-of- 
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.

This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116112 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 21:45:55 +00:00
Jim Grosbach 6313944845 Allow << streaming of MCOperand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116107 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 21:36:13 +00:00
Jim Grosbach bb16824dc3 A few 80 column cleanups 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116069 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 18:13:57 +00:00
Jim Grosbach 9ed2cee105 trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116068 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 18:09:59 +00:00
Jim Grosbach 3e09413c2c Reapply 116059, this time without the fatfingered pasto at the top. 
''const'ify getMachineOpValue() and associated helpers.'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116067 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 17:45:54 +00:00
Jim Grosbach 2cee75a254 Reverting 116059. Bots are unhappy with it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116064 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 17:28:40 +00:00
Jim Grosbach 461caba214 'const'ify getMachineOpValue() and associated helpers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116059 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 16:52:44 +00:00
Jim Grosbach 0f448b5bf6 Add test file for simple ARM binary encodings with MC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116024 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 00:47:59 +00:00
Jim Grosbach 58f38bfa24 Enable binary encoding of some simple instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116022 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-08 00:39:21 +00:00