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2104 Commits

Author SHA1 Message Date
Craig Topper
2dcd718c13 Update CanXFormVExtractWithShuffleIntoLoad to ensure bitcasts of loads only have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150360 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-13 04:30:38 +00:00
Anton Korobeynikov
d4a19b6a72 Add support for implicit TLS model used with MS VC runtime. 
Patch by Kai Nacke!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150307 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-11 17:26:53 +00:00
Craig Topper
39a9e485f2 Fix shuffle lowering code to stop creating temporary DAG nodes to do shuffle mask checks on. This seemed to be confusing things such that vector_shuffle ops to got through to iselection. This is another step towards removing the vector_shuffle handling patterns from isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150296 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-11 06:24:48 +00:00
Elena Demikhovsky
f602040c49 Fixed a bug in printing "cmp" pseudo ops. 
> This IR code
> %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 14)
> fails with assertion:
>
> llc: X86ATTInstPrinter.cpp:62: void llvm::X86ATTInstPrinter::printSSECC(const llvm::MCInst*, unsigned int, llvm::raw_ostream&): Assertion `0 && "Invalid ssecc argument!"' failed.
> 0  llc             0x0000000001355803
> 1  llc             0x0000000001355dc9
> 2  libpthread.so.0 0x00007f79a30575d0
> 3  libc.so.6       0x00007f79a23a1945 gsignal + 53
> 4  libc.so.6       0x00007f79a23a2f21 abort + 385
> 5  libc.so.6       0x00007f79a239a810 __assert_fail + 240
> 6  llc             0x00000000011858d5 llvm::X86ATTInstPrinter::printSSECC(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) + 119

I added the full testing for all possible pseudo-ops of cmp.
I extended X86AsmPrinter.cpp and X86IntelInstPrinter.cpp.

You'l also see lines alignments (unrelated to this fix) in X86IselLowering.cpp from my previous check-in.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150068 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-08 08:37:26 +00:00
Craig Topper
5a313bb7e8 Remove GCC builtins for vpermilp* intrinsics as clang no longer needs them. Custom lower the intrinsics to the vpermilp target specific node and remove intrinsic patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150060 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-08 06:36:57 +00:00
Craig Topper
dbd98a4b1b Add instruction selection for 256-bit VPSHUFD and 128-bit VPERMILPS/VPERMILPD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149968 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-07 06:28:42 +00:00
Chris Lattner
7302d80490 Remove some dead code and tidy things up now that vectors use ConstantDataVector 
instead of always using ConstantVector.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149912 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-06 21:56:39 +00:00
Benjamin Kramer
699ddcbcb3 X86: Don't call malloc for 4 bits. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149866 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-06 12:06:18 +00:00
Craig Topper
d156dc11f9 Add shuffle decoding support for 256-bit pshufd. Merge vpermilp* and pshufd decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149859 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-06 07:17:51 +00:00
Duncan Sands
5b8a1db7ea Persuade GCC that there is nothing worth warning about here (there isn't). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149834 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-05 14:20:11 +00:00
Craig Topper
6d1263acb9 Convert assert(0) to llvm_unreachable in X86 Target directory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149809 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-05 05:38:58 +00:00
Craig Topper
abb94d0687 Convert some assert(0) in default of switch statements to llvm_unreachable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149808 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-05 03:43:23 +00:00
Craig Topper
5b209e84f4 Add target specific node for PMULUDQ. Change patterns to use it and custom lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149807 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-05 03:14:49 +00:00
Craig Topper
a02556679e Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate performs the same calculation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149683 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-03 06:52:33 +00:00
Craig Topper
fa5b70e1d8 Remove unnecessary qualification on 256-bit vector handling in LowerBUILD_VECTOR. Condition was already guaranteed by earlier code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149680 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-03 06:32:21 +00:00
Lang Hames
6e3f7e4913 Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149655 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-03 01:13:49 +00:00
Jakob Stoklund Olesen
478a8a02bc Require non-NULL register masks. 
It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 23:52:57 +00:00
Elena Demikhovsky
0f1ead47a0 Minor change in signature of the getZeroVector() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149601 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 09:20:18 +00:00
Elena Demikhovsky
dcabc7bca9 Optimization for SIGN_EXTEND operation on AVX. 
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149600 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 09:10:43 +00:00
Francois Pichet
1ae52f686c Unbreak the MSVC build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149599 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 08:36:09 +00:00
Lang Hames
50a36f7102 Set EFLAGS correctly in EmitLoweredSelect on X86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149597 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 07:48:37 +00:00
Andrew Trick
922d314e8f Instruction scheduling itinerary for Intel Atom. 
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 23:20:51 +00:00
Mon P Wang
845b1899b6 Avoid creating an extract element to an illegal type after LegalizeTypes has run. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149548 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 22:15:20 +00:00
Chad Rosier
c2348d5c08 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149521 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 18:45:51 +00:00
Elena Demikhovsky
732525758f Shortened code in shuffle masks 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149493 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 10:33:05 +00:00
Elena Demikhovsky
3ae98150e3 Optimization for "truncate" operation on AVX. 
Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149485 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 07:56:44 +00:00
Craig Topper
a1902a18cd Don't create VBROADCAST nodes if any nodes use the chain result from the load. Fixes PR11900. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149478 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 06:51:58 +00:00
Craig Topper
cac50c5ab8 Remove pcmpgt/pcmpeq intrinsics as clang is not using them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149367 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-31 06:52:44 +00:00
Benjamin Kramer
630ecf0f53 Fix refacto. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149269 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-30 20:01:35 +00:00
Douglas Gregor
b2f1b5028c Eliminate narrowing conversion in initializer list, to make C++11 happy 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149254 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-30 16:57:18 +00:00
Benjamin Kramer
9c68354956 X86: Simplify shuffle mask generation code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149248 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-30 15:16:21 +00:00
Craig Topper
cc30006391 Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149232 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-30 07:50:31 +00:00
Craig Topper
86c7c583a3 Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149216 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-30 01:10:15 +00:00
Craig Topper
e566cd0f4d Remove some more patterns by custom lowering intrinsics to target specific nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149052 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-26 07:18:03 +00:00
Chris Lattner
9748479590 fix a bug I introduced in r148929, this is not a splat! 
Thanks to Eli for noticing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148947 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 09:56:22 +00:00
Craig Topper
969ba287cd Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148933 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 06:43:11 +00:00
Chris Lattner
4ca829e895 use ConstantVector::getSplat in a few places. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148929 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 06:02:56 +00:00
Craig Topper
4bb3f34b22 Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148927 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-25 05:37:32 +00:00
Elena Demikhovsky
28d7e71a30 ZERO_EXTEND operation is optimized for AVX. 
v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148803 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 13:54:13 +00:00
Craig Topper
7925e2555d Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148687 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 08:18:28 +00:00
Craig Topper
7fb8b0c5d3 Update more places to use target specific nodes for vector shifts instead of intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148685 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 06:46:22 +00:00
Craig Topper
80e46360e9 Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148684 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-23 06:16:53 +00:00
Craig Topper
1906d32e55 Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148670 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 23:36:02 +00:00
Craig Topper
67609fd0eb Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148667 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 22:42:16 +00:00
Craig Topper
ed2e13d667 Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148664 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 19:15:14 +00:00
Craig Topper
07a276277f Make code a little less verbose. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148651 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 03:07:48 +00:00
Craig Topper
6a32b6f0c0 Remove unused X86 ISD node type defines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148644 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-22 01:15:56 +00:00
Craig Topper
d9ec725db4 Fix PR11819 introduced by r148537. I'd commit the test case, but the generated code is terrible as it gets fully scalarized. Expect a future commit to fix that. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148632 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-21 08:49:33 +00:00
David Blaikie
4d6ccb5f68 More dead code removal (using -Wunreachable-code) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 21:51:11 +00:00
Craig Topper
8f35c13842 Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148537 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-20 09:29:03 +00:00