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22841 Commits

Author SHA1 Message Date
Craig Topper
f4d25a2c46 Change getX86SubSuperRegister to take an MVT::SimpleValueType rather than an EVT and add llvm_unreachable to the switches. Helps it compile to dramatically better code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164919 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-30 19:49:56 +00:00
Bob Wilson
eb1641d54a Add LLVM support for Swift. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-29 21:43:49 +00:00
Bob Wilson
154418cdd8 Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164898 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-29 21:27:31 +00:00
Benjamin Kramer
01e872af25 Shrink TargetAlignElem a bit, we do a lot of searches on them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164897 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-29 19:57:14 +00:00
Akira Hatanaka
93ba059e48 MIPS DSP: other miscellaneous instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164845 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-28 20:50:31 +00:00
Akira Hatanaka
e91ff1d135 MIPS DSP: ADDUH.QB instruction sub-class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164840 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-28 20:16:04 +00:00
Manman Ren
bc96bcdaf9 X86: when replacing SUB with TEST in ISelDAGToDAG, only replace uses of the 
second output of SUB with first output of TEST.

PR13966


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164835 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-28 18:53:24 +00:00
Reed Kotler
c94a38ff17 1. Add load/store words from the stack 
2. As part of this, added assembly format FEXT_RI16_SP_explicit_ins and
moved other lines for FEXT_RI16 formats to be in the right place in the code.
3. Added mayLoad and mayStore assignements for the load/store instructions added and for ones already there that did not have this assignment.
4. Another patch will deal with the problem of load/store byte/halfword to the stack. This is a particular Mips16 problem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164811 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-28 02:26:24 +00:00
Akira Hatanaka
cb39aa05af MIPS DSP: ABSQ_S.PH instruction sub-class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164787 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 19:09:21 +00:00
Akira Hatanaka
23bb38f034 MIPS DSP: SHLL.QB instruction sub-class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164786 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 19:05:08 +00:00
Sylvestre Ledru
94c22716d6 Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 10:14:43 +00:00
Sylvestre Ledru
7e2c793a2b Fix a typo 'iff' => 'if' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 09:59:43 +00:00
Jush Lu
8f50647662 [arm-fast-isel] Add support for ELF PIC. 
This is a preliminary step towards ELF support; currently ARMFastISel hasn't
been used for ELF object files yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164759 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 05:21:41 +00:00
Akira Hatanaka
833f7a5c4b MIPS DSP: rddsp (instruction which reads DSPControl register fields to a GPR). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164756 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 04:08:42 +00:00
Akira Hatanaka
451b0e7b8a MIPS DSP: CMPU.EQ.QB instruction sub-class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164755 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 03:58:34 +00:00
Akira Hatanaka
a216401621 MIPS DSP: ADDU.QB instruction sub-class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164754 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 03:13:59 +00:00
Akira Hatanaka
01f7089bca MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164751 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 02:15:57 +00:00
Akira Hatanaka
2df483efb3 MIPS DSP: all the remaining instructions which read or write accumulators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164750 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 02:11:20 +00:00
Akira Hatanaka
fd89e6ffda MIPS DSP: add support for extract-word instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164749 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 02:05:42 +00:00
Akira Hatanaka
5e69cef21b MIPS DSP: add functions which decode DSP and accumulator registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164748 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 02:01:10 +00:00
Akira Hatanaka
cc46fe591a MIPS DSP: add code necessary for pseudo instruction lowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164747 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 01:59:07 +00:00
Akira Hatanaka
7e105bcc3a MIPS DSP: add bitcast patterns between vectors and int. 
No test cases. These patterns will get tested along with dsp intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164746 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 01:56:38 +00:00
Akira Hatanaka
7509ec18d1 MIPS DSP: add vector load/store patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164744 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-27 01:50:59 +00:00
Bill Wendling
2c18906118 Remove the `hasFnAttr' method from Function. 
The hasFnAttr method has been replaced by querying the Attributes explicitly. No
intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164725 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-26 21:48:26 +00:00
Jim Grosbach
b7abea0840 X86_32: Large Symbol+Offset relocations. 
If the offset is more than 24-bits, it won't fit in a scattered
relocation offset field, so we fall back to using a non-scattered
relocation.

rdar://12358909

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164724 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-26 21:27:45 +00:00
Akira Hatanaka
b500e9249a Add case clauses for returning dsp accumulator encoding values in function 
getMipsRegisterNumbering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164720 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-26 19:27:24 +00:00
Akira Hatanaka
81571d3e0f Add DSP accumulator registers and register class. Remove hi/lo registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164719 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-26 19:25:21 +00:00
Akira Hatanaka
c878f3899c Delete member MipsFunctionInfo::OutArgFIRange and code that accesses it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164718 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-26 19:18:19 +00:00
James Molloy
d6d10ae151 Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164685 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-26 09:48:32 +00:00
Michael Liao
4fa2ddbb94 Add SARX/SHRX/SHLX code generation support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164675 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-26 08:26:25 +00:00
Michael Liao
6bcdb5b903 Add RORX code generation support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164674 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-26 08:24:51 +00:00
Michael Liao
0832a72a66 Add MULX code generation support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164673 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-26 08:22:37 +00:00
Craig Topper
d48bb9316d Remove hasNoAVX method. Can just invert hasAVX instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164664 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-26 06:29:37 +00:00
Michael Liao
4e9485d732 Add 'lock' prefix output support in assembly printer 
- Instead of embedding 'lock' into each mnemonic of atomic
  instructions except 'xchg', we teach X86 assembly printer to output 'lock'
  prefix similar to or consistent with code emitter.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164659 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-26 05:13:44 +00:00
Akira Hatanaka
3757ff1a68 Initialize boolean variables in MipsSubtarget's constructor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164642 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-25 23:07:11 +00:00
Reed Kotler
289b5d7f02 blank line for test commit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164640 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-25 22:34:20 +00:00
Sebastian Pop
1a37d7e807 TargetLowering interface to set/get minimum block entries for jump tables. 
Provide interface in TargetLowering to set or get the minimum number of basic
blocks whereby jump tables are generated for switch statements rather than an
if sequence.

    getMinimumJumpTableEntries() defaults to 4.
    setMinimumJumpTableEntries() allows target configuration.

    This patch changes the default for the Hexagon architecture to 5
    as it improves performance on some benchmarks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164628 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-25 20:35:36 +00:00
Michael Liao
e5e8f7656a Add missing i64 max/min/umax/umin on 32-bit target 
- Turn on atomic6432.ll and add specific test case as well



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164616 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-25 18:08:13 +00:00
Jim Grosbach
fe2d5f8487 ARM: Darwin BL/BLX relocations to out-of-range symbols. 
When a BL/BLX references a symbol in the same translation unit that is
out of range, use an external relocation. The linker will use this to
generate a branch island rather than a direct reference, allowing the
relocation to resolve correctly.

rdar://12359919

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164615 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-25 18:07:17 +00:00
Bob Wilson
a3c3e1f8e2 Consistently specify the assembly variant to MatchInstructionImpl. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164611 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-25 17:19:29 +00:00
Evan Cheng
b1cacc7423 Fix an illegal tailcall opt where the callee returns a double via xmm while caller returns x86_fp80 via st0. rdar://12229511 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164588 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-25 05:32:34 +00:00
Jim Grosbach
fbc21fabae ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'. 
rdar://9795790

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164577 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-25 00:08:13 +00:00
Jim Grosbach
e9525d8624 Mark jump tables in code sections with DataRegion directives. 
Even out-of-line jump tables can be in the code section, so mark them
as data-regions for those targets which support the directives.

rdar://12362871&12362974

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164571 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-24 23:06:27 +00:00
Chad Rosier
2590c2e1e9 Rather then have a wrapper function, have tblgen instantiate the implementation. 
Also remove an unused argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164567 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-24 22:57:55 +00:00
Roman Divacky
5236ab3fdd Specify MachinePointerInfo as refering to the argument value and offset of the 
store when handling byval arguments. Thus preventing reordering of the store
with load with post-RA scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164553 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-24 20:47:19 +00:00
Chad Rosier
00796a1b15 Rather then have a wrapper function, have tblgen instantiate the implementation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164548 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-24 19:32:29 +00:00
NAKAMURA Takumi
d15e2a0857 ARMInstPrinter.cpp: Fix a warning in -Asserts. [-Wunused-variable] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164459 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-22 13:12:28 +00:00
NAKAMURA Takumi
2d67eac2e6 Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164458 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-22 13:12:22 +00:00
Tim Northover
bb5174246b Fix edge cases of ARM shift operands in arith instructions. 
As before with load instructions, oddities like "asr #32", "rrx" could
be printed incorrectly.

Patch by Chris Lidbury.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164456 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-22 11:18:19 +00:00
Tim Northover
93c7c449a1 Fix the handling of edge cases in ARM shifted operands. 
This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.

Patch by Chris Lidbury.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-22 11:18:12 +00:00