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3 Commits

Author SHA1 Message Date
Justin Holewinski
7e6565112b [NVPTX] Rename registers %fl -> %fd and %rl -> %rd 
This matches the internal behavior of NVIDIA tools like libnvvm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213168 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-16 16:26:58 +00:00
Eli Bendersky
85af3e7445 Fix the test: DCE optimized away everything. 
Use volatile store to protect the generated PTX from DCE.

Patch by Jingyue Wu.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206763 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-21 17:23:12 +00:00
Justin Holewinski
a3635eefc7 [NVPTX] Fix bug in stack code generation causes by MC conversion 
We do use a very small set of physical registers, so account for
them in the virtual register encoding between MachineInstr and MC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187799 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 14:13:31 +00:00