Commit Graph

82321 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
1a2a19dd3c Add TargetRegisterClass::getSuperRegIndices().
This is a pointer into one of the tables used by
getMatchingSuperRegClass(). It makes it possible to use a shared
implementation of that function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156121 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 22:49:00 +00:00
Jakob Stoklund Olesen
6a0ed18532 Emit SuperRegMasks as part of the existing SubClassMask arrays.
The RC->getSubClassMask() pointer now points to a sequence of register
class bit masks. The first bit mask is the normal sub-class mask. The
following masks are super-reg class masks used by
getMatchingSuperRegClass().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156120 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 22:48:56 +00:00
Kevin Enderby
2d524b0765 Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
for the assembler and disassembler.  Which were not being set/read correctly
for offsets greater than 22 bits in some cases.

Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 22:41:56 +00:00
Chandler Carruth
9f7af7b748 Factor the logic for testing whether a basic block is viable for code
extraction into a public interface. Also clean it up and apply it more
consistently such that we check for landing pads *anywhere* in the
extracted code, not just in single-block extraction.

This will be used to guide decisions in passes that are planning to
eventually perform a round of code extraction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156114 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 22:26:53 +00:00
Nuno Lopes
cb348b9b45 remove calls to calloc if the allocated memory is not used (it was already being done for malloc)
fix a few typos found by Chad in my previous commit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 22:08:19 +00:00
Sirish Pande
26f61a158b Support for target dependent Hexagon VLIW packetizer.
This patch creates and optimizes packets as per Hexagon ISA rules.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 21:52:53 +00:00
Ted Kremenek
ff9229ecf0 Add rudimentary CMake logic for detecting Graphviz.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156108 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 21:51:05 +00:00
Nuno Lopes
252ef566e8 add support for calloc to objectsize lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156102 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 21:19:58 +00:00
Jakob Stoklund Olesen
1d61f283fa Fix the type of SubClassMask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156084 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 18:17:32 +00:00
Jakob Stoklund Olesen
f92be238d6 Compress tables for getMatchingSuperRegClass().
Many register classes only have a few super-registers, so it is not
necessary to keep individual bit masks for all possible sub-register
indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156083 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 18:14:20 +00:00
Owen Anderson
5e7469647c Add the half type to the LLVM IR vim syntax highlighting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156080 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 17:24:12 +00:00
Silviu Baranga
b422d0b65e Fixed disassembler for vstm/vldm ARM VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 16:38:40 +00:00
Jakob Stoklund Olesen
309076ff76 Don't override subreg functions in targets without subregisters.
Some targets have no sub-registers at all. Use the TargetRegisterInfo
versions of composeSubRegIndices(), getSubClassWithSubReg(), and
getMatchingSuperRegClass() for those targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 16:26:20 +00:00
Sirish Pande
71d56462a1 Extensions of Hexagon V4 instructions.
This adds new instructions for Hexagon V4 architecture.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156071 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 16:18:50 +00:00
Nuno Lopes
a199e01d8e replace 'break's with 'return 0' in visitCallInst code for objectsize, since there is no need to fallback to visitCallSite.
This gives a 0.9% in a test case

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156069 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 16:06:07 +00:00
Duncan Sands
28d95b0a04 Use correct variable in this example. Pointed out by waynix on IRC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156067 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 15:25:19 +00:00
Craig Topper
b607264550 Use 'unsigned' instead of 'int' in a few places dealing with counts of vector elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156060 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 07:26:59 +00:00
Craig Topper
6b28d356c5 Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the lower half correctly. Missed in r155982.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 07:12:59 +00:00
Evan Cheng
d99d68bcee Fix two-address pass's aggressive instruction commuting heuristics. It's meant
to catch cases like:
 %reg1024<def> = MOV r1
 %reg1025<def> = MOV r0
 %reg1026<def> = ADD %reg1024, %reg1025
 r0            = MOV %reg1026

By commuting ADD, it let coalescer eliminate all of the copies. However, there
was a bug in the heuristics where it ended up commuting the ADD in:

 %reg1024<def> = MOV r0
 %reg1025<def> = MOV 0
 %reg1026<def> = ADD %reg1024, %reg1025
 r0            = MOV %reg1026

That did no benefit but rather ensure the last MOV would not be coalesced.

rdar://11355268


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156048 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 01:45:13 +00:00
Andrew Trick
f12f6dff97 Added TargetRegisterInfo::getAllocatableClass.
The ensures that virtual registers always belong to an allocatable class.
If your target attempts to create a vreg for an operand that has no
allocatable register subclass, you will crash quickly.

This ensures that targets define register classes as intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156046 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 01:14:37 +00:00
Bill Wendling
e8cd3f2491 Whitespace cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156034 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 23:43:23 +00:00
Daniel Dunbar
f2c696f016 [docs] Include the Kaleidescope tutorial in the Sphinx docs build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156032 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 22:46:36 +00:00
Owen Anderson
062c0a5b58 Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, just like it now knows for FMULs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156029 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 22:17:40 +00:00
Preston Gurd
c0f0a93936 For Intel Atom, use ILP scheduling always, instead of ILP for 64 bit
and Hybrid for 32 bit, since benchmarks show ILP scheduling is better
most of the time.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 22:02:02 +00:00
Preston Gurd
79bbe855cd Change the Intel Atom detection code to recognize
Lincroft and Medfield.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 21:38:46 +00:00
Owen Anderson
363e4b90c0 Teach DAG combine that multiplication by 1.0 can always be constant folded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156023 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 21:32:35 +00:00
Michael J. Spencer
4599613dec Add tools/lld to .gitignore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156021 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 21:25:32 +00:00
Jim Grosbach
2727930ab4 ARM: Add missing two-operand VBIC aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156019 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 21:11:56 +00:00
Douglas Gregor
f657da2e48 Move llvm-tblgen's StringMatcher into the TableGen library so it can
be used by clang-tblgen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156000 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 17:32:48 +00:00
Anders Waldenborg
8ed9951c3a [llvm-c] Make a few function declarations proper prototypes
This avoids warnings when included in a application that
uses -Wstrict-prototypes. 

e.g: AsmPrinters.def:27:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 16:15:32 +00:00
Preston Gurd
95f0cf0438 This patch continues the work of adding instruction latencies for X86 Atom,
by providing the latencies for the instructions in X86InstrFPStack.td.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 16:03:35 +00:00
Manman Ren
e2849851b2 Revert r155853
The commit is intended to fix rdar://10961709.
But it is the root cause of PR12720.
Revert it for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155992 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 15:24:32 +00:00
Kostya Serebryany
37cb9acac5 [tsan] typo and style (thanks to Nick Lewycky)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155986 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 13:12:19 +00:00
Bill Wendling
55e7098bbc The value held in the vector may be RAUW'ed by some of the canonicalization
methods. Use a weak value handle to keep up with this.
PR12245


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 09:59:45 +00:00
Richard Barton
0a552d611e Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 09:43:18 +00:00
Craig Topper
a9a568a79d Add support for selecting AVX2 vpshuflw and vpshufhw. Add decoding support for AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155982 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 08:03:44 +00:00
John McCall
38dbb60675 Update SmallVector to support move semantics if the host does.
Note that support for rvalue references does not imply support
for the full set of move-related STL operations.

I've preserved support for an odd little thing in insert() where
we're trying to support inserting a new element from an existing
one.  If we actually want to support that, there's a lot more we
need to do:  insert can call either grow or push_back, neither of
which is safe against this particular use pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155979 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 05:39:15 +00:00
John McCall
9679f0f357 Fix unintentional use of operator bool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155978 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 05:39:10 +00:00
Eli Friedman
41827f9ba2 Fix the implementation of MachOObjectFile::isSectionZeroInit so it follows the MachO spec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155976 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02 02:31:28 +00:00
Jim Grosbach
39cc513870 Tidy up. Naming conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 23:21:41 +00:00
Jakub Staszak
dca40aa911 Remove unneeded break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 23:08:16 +00:00
Jakub Staszak
ce00b440f5 Use dyn_cast instead of checking opcode and cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155957 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 23:06:00 +00:00
Jakub Staszak
bf14860572 Remove trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155956 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 23:04:38 +00:00
Bill Wendling
95dd442041 Strip the pointer casts off of allocas so that the selection DAG can find them.
PR10799


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155954 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 22:50:45 +00:00
Sirish Pande
902337092f Target independent Hexagon Packetizer fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155947 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 21:28:30 +00:00
Jim Grosbach
54319e2a8c ARM: Add a few missing add->sub aliases w/ 'w' suffix.
Aliases for adding a negative immediate when using an explicit 'w'
suffix. E.g.,
        adds.w r2, #-16
        adds.w r2, r2, #-16
        addw r2, #-16
        addw r2, #-16
        addw r2, r2, #-16

rdar://11330769

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155946 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 21:17:34 +00:00
Jim Grosbach
94b590f8fa ARM: allow vanilla expressions for movw/movt.
Expressions for movw/movt don't always have an :upper16: or :lower16:
on them and that's ok. When they don't, it's just a plain [0-65536]
immediate result, effectively the same as a :lower16: variant kind.

rdar://10550147

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155941 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 20:43:21 +00:00
Preston Gurd
66413b61f0 This patch marks the X86 floating point stack registers ST0-ST7 as reserved
in order to avoid assertion failures in the register scavenger. The assertion
failures were “Bad machine code: Using an undefined physical register” and
“Bad machine code: MBB exits via unconditional fall-through but its successor
differs from its CFG successor!”.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155930 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 19:50:22 +00:00
Jim Grosbach
686c01854e MC: Unknown assembler directives are now hard errors.
Previously, an unsupported/unknown assembler directive issued a warning.
That's generally unsafe, and inconsistent with the behaviour of pretty
much every system assembler. Now that the MC assemblers are mature
enough to be the default on multiple targets, it's reasonable to
issue errors for these.

For target or platform directives that need to stay warnings, we
should add explicit handlers for them in, e.g., ELFAsmParser.cpp,
DarwinAsmParser.cpp, et. al., and issue the warning there.

rdar://9246275

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155926 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 18:38:27 +00:00
Jim Grosbach
25c7b6e0df MC: Remove errant EatToEndOfStatement() in asm parser.
The caller is already responsible for eating any additional input on the
line. Putting an additional EatToEndOfStatement() in ParseStatement()
causes an entire extra statement to be consumed when treating warnings
as errors. For example, test/MC/macros.s will assert() because the
.endmacro directive is missed as a result.

rdar://11355843

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155925 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-01 18:38:24 +00:00