Richard Osborne 
							
						 
					 
					
						
						
							
						
						e8f3533323 
					 
					
						
						
							
							Add XCore intrinsics for initializing / starting / synchronizing threads.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128633  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-03-31 15:13:13 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						11bd0784d9 
					 
					
						
						
							
							Add XCore intrinsic for setpsc.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127821  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-03-17 18:42:05 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						e17139b3e9 
					 
					
						
						
							
							Add XCore intrinsics for setclk, setrdy.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127761  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-03-16 21:56:00 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						bb057453db 
					 
					
						
						
							
							Add checkevent intrinsic to check if any resources owned by the current thread  
						
						... 
						
						
						
						can event.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127741  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-03-16 18:34:00 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						8ae8cf4559 
					 
					
						
						
							
							On the XCore the scavenging slot should be closest to the SP.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127680  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-03-15 15:10:11 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						5aad8b3e78 
					 
					
						
						
							
							Add XCore intrinsics for getps, setps, setsr and clrsr.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127678  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-03-15 13:45:47 +00:00 
						 
				 
			
				
					
						
							
							
								Benjamin Kramer 
							
						 
					 
					
						
						
							
						
						7bff3e7c1b 
					 
					
						
						
							
							Fix mistyped CHECK lines.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127366  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-03-09 22:07:31 +00:00 
						 
				 
			
				
					
						
							
							
								Joerg Sonnenberger 
							
						 
					 
					
						
						
							
						
						89e0f386f3 
					 
					
						
						
							
							Be nice to Xcore and the XMOS assembler and avoid quoting section names  
						
						... 
						
						
						
						that contain only letters, digits and the characters "_" and ".".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127028  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-03-04 20:03:14 +00:00 
						 
				 
			
				
					
						
							
							
								Joerg Sonnenberger 
							
						 
					 
					
						
						
							
						
						ea83b13350 
					 
					
						
						
							
							Bug#9033: For the ELF assembler output, always quote the section name.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126963  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-03-03 22:31:08 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						21d7eb3f3b 
					 
					
						
						
							
							Add XCore intrinsic for eeu instruction.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126384  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-02-24 13:39:18 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						d04b4937d1 
					 
					
						
						
							
							Add XCore intrinsic for clre instruction.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126322  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-02-23 18:52:05 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						9935bd0819 
					 
					
						
						
							
							Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable  
						
						... 
						
						
						
						events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126320  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-02-23 18:35:59 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						292f62e06f 
					 
					
						
						
							
							Add XCore intrinsic for the setv instruction.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126315  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-02-23 16:46:37 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						2a2cb28526 
					 
					
						
						
							
							Add XCore intrinsic for settw instruction.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126313  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-02-23 14:45:03 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						d83318450b 
					 
					
						
						
							
							Add XCore intrinsics for various instructions on ports.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126132  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-02-21 18:23:30 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						59982f3ffc 
					 
					
						
						
							
							Add intrinsic for setc instruction on the XCore.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125186  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-02-09 13:22:12 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						17c1e51d22 
					 
					
						
						
							
							Add XCore intrinsics for resource instructions.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124794  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-02-03 13:14:25 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						ff0c5014b2 
					 
					
						
						
							
							Add support for trampolines on the XCore.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124722  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-02-02 14:57:41 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						4e3740ee6d 
					 
					
						
						
							
							Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124587  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-01-31 17:41:44 +00:00 
						 
				 
			
				
					
						
							
							
								Rafael Espindola 
							
						 
					 
					
						
						
							
						
						1c10db3da9 
					 
					
						
						
							
							Update tests.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123591  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2011-01-16 18:02:57 +00:00 
						 
				 
			
				
					
						
							
							
								Devang Patel 
							
						 
					 
					
						
						
							
						
						afeaae7a94 
					 
					
						
						
							
							If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121059  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-12-06 22:39:26 +00:00 
						 
				 
			
				
					
						
							
							
								Evan Cheng 
							
						 
					 
					
						
						
							
						
						44be1a8d66 
					 
					
						
						
							
							Enable machine sinking critical edge splitting. e.g.  
						
						... 
						
						
						
						define double @foo(double %x, double %y, i1 %c) nounwind {
  %a = fdiv double %x, 3.2
  %z = select i1 %c, double %a, double %y
  ret double %z
}
Was:
_foo:
        divsd   LCPI0_0(%rip), %xmm0
        testb   $1, %dil
        jne     LBB0_2
        movaps  %xmm1, %xmm0
LBB0_2:
        ret
Now:
_foo:
        testb   $1, %dil
        je      LBB0_2
        divsd   LCPI0_0(%rip), %xmm0
        ret
LBB0_2:
        movaps  %xmm1, %xmm0
        ret
This avoids the divsd when early exit is taken.
rdar://8454886
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114372  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-09-20 22:52:00 +00:00 
						 
				 
			
				
					
						
							
							
								Dan Gohman 
							
						 
					 
					
						
						
							
						
						9f23dee08c 
					 
					
						
						
							
							Start function numbering at 0.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101638  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-04-17 16:29:15 +00:00 
						 
				 
			
				
					
						
							
							
								Dale Johannesen 
							
						 
					 
					
						
						
							
						
						b39b7e5ebf 
					 
					
						
						
							
							Split big test into multiple directories to cater to  
						
						... 
						
						
						
						those who don't build all targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100688  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-04-07 20:43:35 +00:00 
						 
				 
			
				
					
						
							
							
								Chris Lattner 
							
						 
					 
					
						
						
							
						
						3b9d6216a4 
					 
					
						
						
							
							fix AsmPrinter::GetBlockAddressSymbol to always return a unique  
						
						... 
						
						
						
						label instead of trying to form one based on the BB name (which
causes collisions if the name is empty).  This fixes PR6608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98495  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-03-14 17:53:23 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						79a73fbeb3 
					 
					
						
						
							
							Add dag combine to simplify lmul(x, 0, a, b)  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98258  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-03-11 16:26:35 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						850f1cd3c0 
					 
					
						
						
							
							Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit  
						
						... 
						
						
						
						expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all
operands are zero extended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98168  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-03-10 18:12:27 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						2dacd1e987 
					 
					
						
						
							
							Fold add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if the intermediate  
						
						... 
						
						
						
						results are unused elsewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98157  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-03-10 16:19:31 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						a2cc0613d0 
					 
					
						
						
							
							Prefer LMUL to MACCU as LMUL has no tied operands.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98153  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-03-10 13:27:10 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						a7e78402b8 
					 
					
						
						
							
							Custom lower (S|U)MUL_LOHI -> MACC(S|U)  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98152  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-03-10 13:20:07 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						ebc64cf780 
					 
					
						
						
							
							Lower add (mul a, b), c into MACCU / MACCS nodes which translate  
						
						... 
						
						
						
						directly to the maccu / maccs instructions. We handle this in
ExpandADDSUB since after type legalisation it is messy to
recognise these operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98150  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-03-10 11:41:08 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						1250ac8a09 
					 
					
						
						
							
							Convert test to FileCheck.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98148  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-03-10 11:24:03 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						ad4f66c76f 
					 
					
						
						
							
							In cases where the carry / borrow unused converted ladd / lsub  
						
						... 
						
						
						
						to an add or a sub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98059  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-03-09 16:34:25 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						7b871b3464 
					 
					
						
						
							
							Add DAG combine for ladd / lsub.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98057  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-03-09 16:07:47 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						d712783492 
					 
					
						
						
							
							Fix XCoreTargetLowering::isLegalAddressingMode() to handle VoidTy.  
						
						... 
						
						
						
						Previously LoopStrengthReduce would sometimes be unable to find
a legal formula, causing an assertion failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97226  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-02-26 16:44:51 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						78700b0c55 
					 
					
						
						
							
							Lower BR_JT on the XCore to a jump into a series of jump instructions.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96942  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-02-23 13:25:07 +00:00 
						 
				 
			
				
					
						
							
							
								Chris Lattner 
							
						 
					 
					
						
						
							
						
						a34103f6fa 
					 
					
						
						
							
							convert the last 3 targets to use EmitFunctionBody() now that  
						
						... 
						
						
						
						it has before/end body hooks.
 lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp |   49 ++-----------
 lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp   |   87 ++++++------------------
 lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp |   56 +++------------
 test/CodeGen/XCore/ashr.ll                      |    2 
 4 files changed, 48 insertions(+), 146 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94741  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-01-28 06:22:43 +00:00 
						 
				 
			
				
					
						
							
							
								Dan Gohman 
							
						 
					 
					
						
						
							
						
						aceba31b7a 
					 
					
						
						
							
							Delete useless trailing semicolons.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92740  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2010-01-05 17:55:26 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						bea7df56ce 
					 
					
						
						
							
							Add XCore support for indirectbr / blockaddress.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89273  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2009-11-18 23:20:42 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						13c4fabf99 
					 
					
						
						
							
							Add XCore support for arbitrary-sized aggregate returns.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88802  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2009-11-14 19:33:35 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						c96c8e0e81 
					 
					
						
						
							
							Add some peepholes for signed comparisons using ashr X, X, 32.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83549  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2009-10-08 15:38:17 +00:00 
						 
				 
			
				
					
						
							
							
								Dan Gohman 
							
						 
					 
					
						
						
							
						
						fce288fc91 
					 
					
						
						
							
							Eliminate more uses of llvm-as and llvm-dis.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2009-09-09 00:09:15 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						1123135dbf 
					 
					
						
						
							
							Add support for mergeable sections back into the XCore backend.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79368  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2009-08-18 21:14:31 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						a9e8334877 
					 
					
						
						
							
							Put data with relocations in the same sections as data without relocations.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79351  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2009-08-18 17:58:17 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						2a5e23b44d 
					 
					
						
						
							
							Update getSectionForConstant() to to allow mergable sections to be nulled out  
						
						... 
						
						
						
						if not supported by the ELF subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79249  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2009-08-17 16:37:11 +00:00 
						 
				 
			
				
					
						
							
							
								Chris Lattner 
							
						 
					 
					
						
						
							
						
						760e24cd05 
					 
					
						
						
							
							use XCore-specific section with xcore specific cp/dp flags to restore  
						
						... 
						
						
						
						support for globals going into the appropriate sections with the flags.
This hopefully finishes unbreaking the previous behavior that I broke before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79079  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2009-08-15 06:09:35 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						d558ea5e0a 
					 
					
						
						
							
							Add extra SEXT pattern.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77920  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2009-08-02 22:45:24 +00:00 
						 
				 
			
				
					
						
							
							
								Chris Lattner 
							
						 
					 
					
						
						
							
						
						a87dea4f8c 
					 
					
						
						
							
							switch off of 'Section' onto MCSection.  We're not properly using  
						
						... 
						
						
						
						MCSection subclasses yet, but this is a step in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77708  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2009-07-31 18:48:30 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						e23e0976c7 
					 
					
						
						
							
							Add tests for handling of globals and tls on the XCore. These currently fail  
						
						... 
						
						
						
						but pass when run against r76652.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76923  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2009-07-24 00:38:20 +00:00 
						 
				 
			
				
					
						
							
							
								Richard Osborne 
							
						 
					 
					
						
						
							
						
						db9e697725 
					 
					
						
						
							
							Combine an unaligned store of unaligned load into a memmove.  
						
						... 
						
						
						
						git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75908  91177308-0d34-0410-b5e6-96231b3b80d8 
						
						
					 
					
						2009-07-16 12:50:48 +00:00