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Author SHA1 Message Date
Che-Liang Chiou
f987425657 tblgen: add preprocessor as a separate mode 
This patch adds a preprocessor that can expand nested for-loops for
saving some copy-n-paste in *.td files.

The preprocessor is not yet integrated with TGParser, and so it has
no direct effect on *.td inputs.  However, you may preprocess an td
input (and only preprocess it).

To test the proprecessor, type:
  tblgen -E -o $@ $<



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141079 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 15:14:51 +00:00
Nadav Rotem
34804c4f47 Set operation actions to legal types only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141075 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 12:05:35 +00:00
Nadav Rotem
e8783096d2 Operations should be custom lowered only if their type is legal. 
Test: CellSPU/v2i32.ll when running with -promote-elements



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141074 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 10:03:32 +00:00
Nick Lewycky
e97728ecf8 The product of two chrec's can always be represented as a chrec. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141066 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 06:51:26 +00:00
Craig Topper
6744a17dcf Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 06:30:42 +00:00
Andrew Trick
f143b79b78 LSR should avoid redundant edge splitting. 
This handles the case in which LSR rewrites an IV user that is a phi and
splits critical edges originating from a switch.
Fixes <rdar://problem/6453893> LSR is not splitting edges "nicely"


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 03:50:44 +00:00
Andrew Trick
2aeb8027d6 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141058 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 03:34:49 +00:00
Rafael Espindola
b3c4e26dc5 Remove last references to hotpatch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141057 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 03:08:43 +00:00
Peter Collingbourne
e97552e850 Exclude libLLVMTableGen.a from the shared library 
Unbreaks tools for --enable-shared build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141052 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 00:30:34 +00:00
Bill Wendling
da7e6a9c88 Generic cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141050 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 00:16:40 +00:00
Andrew Trick
d974ea22a5 Unit test for r140919, loop unroll heuristics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141049 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-04 00:07:02 +00:00
Jim Grosbach
3207e6c6b7 Tidy up. These tests are covered in the .s file tests now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 23:40:13 +00:00
Jim Grosbach
9d39036f62 ARM assembly parsing and encoding for VMOV immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 23:38:36 +00:00
Jim Grosbach
2a3f19d7e3 Tidy up. 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141043 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 23:03:26 +00:00
Bill Wendling
ff4216a68a Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 22:44:15 +00:00
Bill Wendling
f8520d564c Don't carry over the dispatchsetup hack from the old system. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141040 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 22:42:40 +00:00
Jim Grosbach
68259145d9 ARM parsing/encoding for VCMP/VCMPE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 22:30:24 +00:00
Nick Lewycky
03dd4e8bd3 Fix typo in comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141032 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:30:08 +00:00
Bill Wendling
f7e4aefd0f Check-pointing the new SjLj EH lowering. 
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141031 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:25:38 +00:00
Akira Hatanaka
bbb47b320d Move CHECK after entry label. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141030 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:24:30 +00:00
Akira Hatanaka
43e43f7d8b Add support for 64-bit logical NOR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141029 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:23:18 +00:00
Akira Hatanaka
2d57088ff0 Add support for 64-bit count leading ones and zeros instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:16:50 +00:00
Bill Wendling
631d11765b Move the grabbing of the jump buffer into the caller function, eliminating the need for returning a std::pair. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141026 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:15:28 +00:00
Jim Grosbach
5cd5ac6ad4 ARM assembly parsing and encoding for VMRS/FMSTAT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:12:43 +00:00
Akira Hatanaka
dda4a07cd8 Add support for 64-bit divide instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 21:06:13 +00:00
Devang Patel
0e6a24d92a Add C api for Instruction->eraseFromParent(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141023 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:59:18 +00:00
Jim Grosbach
f8bf43ec99 Update test for 141010. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:58:08 +00:00
Jim Grosbach
b95ed6ec46 Thumb2 ADD/SUB can take SP as a destination register. 
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141020 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:51:59 +00:00
Akira Hatanaka
2ad766851d Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer 
registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141019 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:38:08 +00:00
Akira Hatanaka
04d3762ff1 Add support for 64-bit integer multiply instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141017 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 20:01:11 +00:00
Akira Hatanaka
36787939b2 Add definitions of instructions which move values between 64-bit integer 
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 19:28:44 +00:00
Bob Wilson
ae59e8cd4d Find the strip tool that works with the specified SDKROOT. rdar://10165908 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 18:48:16 +00:00
Jim Grosbach
c82c101147 Tidy up a bit. Formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141010 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 17:59:31 +00:00
Craig Topper
581fe82c84 Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 17:28:23 +00:00
Eric Christopher
8cf5e74a9c Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141005 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 15:49:20 +00:00
Eric Christopher
1aeb7ac624 Typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141004 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 15:49:16 +00:00
Rafael Espindola
25456ef74c Add the returns_twice attribute to LLVM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141001 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 14:45:37 +00:00
Craig Topper
04c5be9f12 Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 08:14:29 +00:00
Craig Topper
04b0b34b3a Test updates that were supposed to go with r140993. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140994 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 07:53:59 +00:00
Craig Topper
7b22976de3 Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140993 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 07:51:09 +00:00
Nick Lewycky
1cbae18cf6 Reapply r140979 with fix! We never did get a testcase, but careful review of the 
logic by David Meyer revealed this bug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140992 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 07:10:45 +00:00
Torok Edwin
48488a64fa attempt to fix ocaml bindings: landing pads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140991 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 06:41:46 +00:00
Nick Lewycky
4fcc80a486 Revert r140979 due to reports of bootstrap failure. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140980 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 05:14:59 +00:00
Nick Lewycky
8fde4f5842 Add one more case we compute a max trip count. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140979 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-03 01:03:57 +00:00
Craig Topper
82f131a017 Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 21:08:12 +00:00
Craig Topper
146c6d77f0 Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140971 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 16:56:09 +00:00
Nick Lewycky
11357d4f40 Add a new icmp+select optz'n. Also shows off the load(cst) folding added in 
r140966.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140969 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 10:37:37 +00:00
Nick Lewycky
267236ade3 Enhance a couple places where we were doing constant folding of instructions, 
but not load instructions. Noticed by inspection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140966 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 09:12:55 +00:00
Craig Topper
42fbe9aa06 Fix typo in r140954. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140962 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 04:54:26 +00:00
Ted Kremenek
4f101db885 Make canonicalization of ImmutableSetRef::asImmutableSet() semi-explicit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140959 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-02 01:47:07 +00:00