Commit Graph

13806 Commits

Author SHA1 Message Date
David Majnemer
cc714e2142 Move the personality function from LandingPadInst to Function
The personality routine currently lives in the LandingPadInst.

This isn't desirable because:
- All LandingPadInsts in the same function must have the same
  personality routine.  This means that each LandingPadInst beyond the
  first has an operand which produces no additional information.

- There is ongoing work to introduce EH IR constructs other than
  LandingPadInst.  Moving the personality routine off of any one
  particular Instruction and onto the parent function seems a lot better
  than have N different places a personality function can sneak onto an
  exceptional function.

Differential Revision: http://reviews.llvm.org/D10429

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239940 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 20:52:32 +00:00
Ahmed Bougacha
4412d4b51f [CodeGenPrepare] Generalize inserted set from truncs to any inst.
It's been used before to avoid infinite loops caused by separate CGP
optimizations undoing one another.  We found one more such issue
caused by r238054.  To avoid it, generalize the "InsertedTruncs"
set to any inst, and use it to avoid touching those again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239938 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 20:44:32 +00:00
Colin LeMahieu
6fc90b32e3 [Hexagon] Adding a number of other tests for min/max instructions and loading i1s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239935 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 20:29:33 +00:00
Colin LeMahieu
7540f2c60a [Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239917 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 17:19:05 +00:00
Igor Breger
a066970605 AVX-512: cvtusi2ss/d intrinsics.
Change builtin function name and signature ( add third parameter - rounding mode ).
Added tests for intrinsics.

Differential Revision: http://reviews.llvm.org/D10473

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239888 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 07:23:57 +00:00
Matthias Braun
e460807bcd Revert "AArch64: Use CMP;CCMP sequences for and/or/setcc trees."
The patch triggers a miscompile on SPEC 2006 403.gcc with the (ref)
200.i and scilab.i inputs. I opened PR23866 to track analysis of this.

This reverts commit r238793.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239880 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 04:02:32 +00:00
Colin LeMahieu
360661f1d1 [Hexagon] Adding MC ELF streamer and updating addend relocation test which shows correct ELF symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239876 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-17 03:06:16 +00:00
Sanjay Patel
f0cbe326ff Add some tests based on PR21711
These were originally added in r227242,
but that patch was reverted because it
caused a failure on AArch64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239860 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 22:37:50 +00:00
Simon Pilgrim
e2d3e4467e [X86][SSE] Vectorize v2i32 to v2f64 conversions
This patch enables support for the conversion of v2i32 to v2f64 to use the CVTDQ2PD xmm instruction and stay on the SSE unit instead of scalarizing, sign extending to i64 and using CVTSI2SDQ scalar conversions.

Differential Revision: http://reviews.llvm.org/D10433

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239855 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 21:40:28 +00:00
Philip Reames
489a03c754 Reapply 239795 - [InstCombine] Propagate non-null facts to call parameters
The original change broke clang side tests.  I will be submitting those momentarily.  This change includes post commit feedback on the original change from from Pete Cooper.

Original Submission comments:
If a parameter to a function is known non-null, use the existing parameter attributes to record that fact at the call site. This has no optimization benefit by itself - that I know of - but is an enabling change for http://reviews.llvm.org/D9129.

Differential Revision: http://reviews.llvm.org/D9132



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239849 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 20:24:25 +00:00
Igor Laevsky
bfbac55e4e [Statepoints] Test only change. Check that statepoint lowering didn't generate more than expected amount of spills.
See http://reviews.llvm.org/D10402 for related discussion.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239842 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 19:07:05 +00:00
Alex Lorenz
d8a0ff34d9 MIR Parser: Report an error when a machine function doesn't have a corresponding function.
This commit reports an error when a machine function from a MIR file that contains
LLVM IR can't find a function with the same name in the loaded LLVM IR module.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10468


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239831 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 17:06:29 +00:00
Kit Barton
1b26bfbef1 Properly handle the mftb instruction.
The mftb instruction was incorrectly marked as deprecated in the PPC
Backend. Instead, it should not be treated as deprecated, but rather be
implemented using the mfspr instruction. A similar patch was put into GCC last
year. Details can be found at:

https://sourceware.org/ml/binutils/2014-11/msg00383.html.
This change will replace instances of the mftb instruction with the mfspr
instruction for all CPUs except 601 and pwr3. This will also be the default
behaviour.

Additional details can be found in:

https://llvm.org/bugs/show_bug.cgi?id=23680

Phabricator review: http://reviews.llvm.org/D10419


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239827 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 16:01:15 +00:00
Matt Arsenault
5202cab841 Revert "Revert "Fix merges of non-zero vector stores""
Reapply r239539. Don't assume the collected number of
stores is the same vector size. Just take the first N
stores to fill the vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239825 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 15:51:48 +00:00
Asaf Badouh
7ae3494732 [AVX512] add integer min/max intrinsics support.
review:
http://reviews.llvm.org/D10439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239806 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 08:39:27 +00:00
NAKAMURA Takumi
4ec9824e8c Disable llvm/test/CodeGen/MIR/machine-function.mir on x86 msc18 for now. Investigating.
The emission was as below;

  ---
  name:            foo
  alignment:       31428584
  exposesReturnsTwice: true
  hasInlineAsm:    false
  ...
  ---
  name:            bar
  alignment:       1701667182
  exposesReturnsTwice: false
  hasInlineAsm:    false
  ...
  ---
  name:            func
  alignment:       8
  exposesReturnsTwice: false
  hasInlineAsm:    false
  ...
  ---
  name:            func2
  alignment:       16
  exposesReturnsTwice: true
  hasInlineAsm:    true
  ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239805 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 06:57:35 +00:00
Elena Demikhovsky
05e61f7113 X86: optimized i64 vector multiply with constant
When we multiply two 64-bit vectors, we extract lower and upper part and use the PMULUDQ instruction.
When one of the operands is a constant, the upper part may be zero, we know this at compile time.
Example: %a = mul <4 x i64> %b, <4 x i64> < i64 5, i64 5, i64 5, i64 5>.
I'm checking the value of the upper part and prevent redundant "multiply", "shift" and "add" operations.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239802 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 06:07:24 +00:00
Philip Reames
f8848a8149 Revert 239795
I forgot to update some clang test cases.  I'll fix and resubmit tomorrow.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239800 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 01:20:53 +00:00
Ahmed Bougacha
819a6b7d4b [AArch64] Generalize extract-high DUP extension to MOVI/MVNI.
These are really immediate DUPs, and suffer from the same problem
with long instructions with a high/2 variant (e.g. smull).

By extending a MOVI (or DUP, before this patch), we can avoid an ext
on the other operand of the long instruction, e.g. turning:
    ext.16b v0, v0, v0, #8
    movi.4h v1, #0x53
    smull.4s  v0, v0, v1
into:
    movi.8h v1, #0x53
    smull2.4s  v0, v0, v1

While there, add a now-necessary combine to fold (VT NVCAST (VT x)).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239799 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 01:18:14 +00:00
Ahmed Bougacha
d4521f1dd5 [AArch64] Robustize neon-2velem-high test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239798 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 01:05:39 +00:00
Philip Reames
6025d734a8 [InstCombine] Propagate non-null facts to call parameters
If a parameter to a function is known non-null, use the existing parameter attributes to record that fact at the call site. This has no optimization benefit by itself - that I know of - but is an enabling change for http://reviews.llvm.org/D9129.

Differential Revision: http://reviews.llvm.org/D9132



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239795 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 00:43:54 +00:00
Alex Lorenz
00b6413c97 MIR Serialization: Print and parse simple machine function attributes.
This commit serializes the simple, scalar attributes from the 
'MachineFunction' class.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10449


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239790 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-16 00:10:47 +00:00
Alex Lorenz
034945e8fe MIR Serialization: Create dummy functions when the MIR file doesn't have LLVM IR.
This commit creates a dummy LLVM IR function with one basic block and an unreachable
instruction for each parsed machine function when the MIR file doesn't have LLVM IR.
This change is required as the machine function analysis pass creates machine
functions only for the functions that are defined in the current LLVM module.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10135


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239778 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 23:07:38 +00:00
Alex Lorenz
185789e9a0 MIR Serialization: Report an error when machine functions have the same name.
This commit reports an error when the MIR parser encounters a machine
function with the name that is the same as the name of a different
machine function.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10130


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239774 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 22:23:23 +00:00
Colin LeMahieu
0d6057a14d [Hexagon] Using readobj rather than objdump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239770 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 21:57:41 +00:00
Colin LeMahieu
c1344684c9 [Hexagon] PC-relative offsets are relative to packet start rather than the offset of the relocation. Set relocation addend and check it's correct in the ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239769 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 21:52:13 +00:00
Simon Pilgrim
b1ce237a80 [X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239767 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 21:49:31 +00:00
Alex Lorenz
a15d888abf MIR Serialization: Connect the machine function analysis pass to the MIR parser.
This commit connects the machine function analysis pass (which creates machine
functions) to the MIR parser, which will initialize the machine functions 
with the state from the MIR file and reconstruct the machine IR.

This commit introduces a new interface called 'MachineFunctionInitializer',
which can be used to provide custom initialization for the machine functions.

This commit also introduces a new diagnostic class called 
'DiagnosticInfoMIRParser' which is used for MIR parsing errors.
This commit modifies the default diagnostic handling in LLVMContext - now the
the diagnostics are printed directly into llvm::errs() so that the MIR parsing 
errors can be printed with colours.  

Reviewers: Justin Bogner

Differential Revision: http://reviews.llvm.org/D9928


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239753 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 20:30:22 +00:00
Sanjoy Das
0f73200fd2 Add "REQUIRES: asserts" to test case that uses -debug-only
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239748 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 20:05:38 +00:00
Sanjoy Das
8d5b28507b [CodeGen] Add a pass to fold null checks into nearby memory operations.
Summary:
This change adds an "ImplicitNullChecks" target dependent pass.  This
pass folds null checks into memory operation using the FAULTING_LOAD
pseudo-op introduced in previous patches.

Depends on D10197
Depends on D10199
Depends on D10200

Reviewers: reames, rnk, pgavlin, JosephTremoulet, atrick

Reviewed By: atrick

Subscribers: ab, JosephTremoulet, llvm-commits

Differential Revision: http://reviews.llvm.org/D10201

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239743 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 18:44:27 +00:00
Evgeny Astigeevich
2ecc72cc58 On behalf of Alexandros Lamprineas:
LLVM targeting aarch64 doesn't correctly produce aligned accesses for non-aligned
data at -O0/fast-isel (-mno-unaligned-access).
The root cause seems to be in fast-isel not producing unaligned access correctly
for -mno-unaligned-access.

The patch just aborts fast-isel for loads and stores when -mno-unaligned-access is
present. 
The regression test is updated to check this new test case (-mno-unaligned-access 
together with fast-isel).

Differential Revision: http://reviews.llvm.org/D10360



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239732 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 15:48:44 +00:00
Hao Liu
5e1ea386d4 [AArch64] Delete two empty files, which should be removed by r239713.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239715 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 02:56:40 +00:00
Hao Liu
5ab48a2f69 [AArch64] Revert r239711 again. We need to discuss how to share code between AArch64 and ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239713 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 01:56:40 +00:00
Hao Liu
6024ab3b8f [AArch64] Match interleaved memory accesses into ldN/stN instructions.
Re-commit after adding "-aarch64-neon-syntax=generic" to fix the failure on OS X.
This patch was firstly committed in r239514, then reverted in r239544 because of a syntax incompatible failure on OS X.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239711 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 01:35:49 +00:00
Igor Breger
17ae2138b0 AVX-512: Implemented DAG lowering for shuff62x2/shufi62x2 instuctions ( Shuffle Packed Values at 128-bit Granularity )
Tests added , vector-shuffle-512-v8.ll test re-generated.

Differential Revision: http://reviews.llvm.org/D10300

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239697 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-14 13:07:47 +00:00
Igor Breger
6ea3ad7e6e AVX-512: Implemented cvtsi2ss/d cvtusi2ss/d instructions with round control for KNL.
Added intrinsics for cvtsi2ss/d instructions.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D10430

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239694 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-14 12:44:55 +00:00
Colin LeMahieu
3a36996b73 [Hexagon] Adding some codegen tests and updating some to match spec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239690 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 21:46:39 +00:00
Simon Pilgrim
4692cb1303 [DAGCombiner] Added BSWAP(BSWAP(x)) -> x combine pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239682 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 16:25:12 +00:00
Simon Pilgrim
d8b27b1cb1 [DAGCombiner] Added BSWAP vector constant folding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239675 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 14:08:15 +00:00
Tom Stellard
953c681473 R600 -> AMDGPU rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:28:10 +00:00
Tim Northover
31b680fa24 AArch64: map bare-metal arm64-macho triple to MachO MC layer.
Far better than an assertion about expecting ELF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239647 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 23:37:11 +00:00
Tom Stellard
f28da43112 R600/SI: Add assembler support for FLAT instructions
- Add glc, slc, and tfe operands to flat instructions
- Add missing flat instructions
- Fix the encoding of flat_load_dwordx3 and flat_store_dwordx3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239637 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 20:47:06 +00:00
Colin LeMahieu
53aa3e0444 [Hexagon] Making intrinsic tests agnostic to register allocation. Narrowing intrinsic parameters to appropriate width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239634 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 19:57:32 +00:00
Rafael Espindola
a66840f18d Don't depend on the interleaving of stdout and stderr.
That can change as we change the buffering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239602 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 12:20:03 +00:00
John Brawn
14d0411acb [ARM] Disabling vfp4 should disable fp16
ARMTargetParser::getFPUFeatures should disable fp16 whenever it
disables vfp4, as otherwise something like -mcpu=cortex-a7 -mfpu=none
leaves us with fp16 enabled (though the only effect that will have is
a wrong build attribute).

Differential Revision: http://reviews.llvm.org/D10397


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239599 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 09:38:51 +00:00
Reid Kleckner
2bd0221fa4 [WinEH] Put finally pointers in the handler scope table field
We were putting them in the filter field, which is correct for 64-bit
but wrong for 32-bit.

Also switch the order of scope table entry emission so outermost entries
are emitted first, and fix an obvious state assignment bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239574 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 23:37:18 +00:00
Reid Kleckner
3e16bd3aaf [WinEH] Create an llvm.x86.seh.exceptioninfo intrinsic
This intrinsic is like framerecover plus a load. It recovers the EH
registration stack allocation from the parent frame and loads the
exception information field out of it, giving back a pointer to an
EXCEPTION_POINTERS struct. It's designed for clang to use in SEH filter
expressions instead of accessing the EXCEPTION_POINTERS parameter that
is available on x64.

This required a minor change to MC to allow defining a label variable to
another absolute framerecover label variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239567 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 22:32:23 +00:00
Peter Collingbourne
6170134a1f Object: Prepend __imp_ when mangling a dllimport symbol in IRObjectFile.
We cannot prepend __imp_ in the IR mangler because a function reference may
be emitted unmangled in a constant initializer. The linker is expected to
resolve such references to thunks. This is covered by the new test case.

Strictly speaking we ought to emit two undefined symbols, one with __imp_ and
one without, as we cannot know which symbol the final object file will refer
to. However, this would require rather intrusive changes to IRObjectFile,
and lld works fine without it for now.

This reimplements r239437, which was reverted in r239502.

Differential Revision: http://reviews.llvm.org/D10400

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239560 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 21:42:18 +00:00
Rafael Espindola
688e7b3049 This reverts commit r239529 and r239514.
Revert "[AArch64] Match interleaved memory accesses into ldN/stN instructions."
Revert "Fixing MSVC 2013 build error."

The  test/CodeGen/AArch64/aarch64-interleaved-accesses.ll test was failing on OS X.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239544 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 17:30:33 +00:00
Reid Kleckner
cd354fa84d Revert "Fix merges of non-zero vector stores"
This reverts commit r239539.

It was causing SDAG assertions while building freetype.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239543 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 17:25:24 +00:00