Evan Cheng
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8442d00a0e
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rev, rev16, and revsh do not set CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78561 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-08-10 07:58:45 +00:00 |
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Evan Cheng
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0d3007bb32
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Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78560 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-08-10 07:20:37 +00:00 |
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Evan Cheng
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26cc252a43
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CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78559 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-08-10 06:57:42 +00:00 |
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Evan Cheng
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e8af1f9afe
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Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78550 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-08-10 02:37:24 +00:00 |
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Evan Cheng
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a56c57e5f0
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Add support to convert 32-bit instructions to 16-bit non-two-address ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78540 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-08-09 19:17:19 +00:00 |
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Evan Cheng
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3eff16e27a
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Add a skeleton Thumb2 instruction size reduction pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78456 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-08-08 03:21:23 +00:00 |
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