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https://github.com/c64scene-ar/llvm-6502.git
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6f6ca40ef0
Reapply r242500 now that the swift schedmodel includes LDRLIT. This is mostly done to disable the PostRAScheduler which optimizes for instruction latencies which isn't a good fit for out-of-order architectures. This also allows to leave out the itinerary table in swift in favor of the SchedModel ones. This change leads to performance improvements/regressions by as much as 10% in some benchmarks, in fact we loose 0.4% performance over the llvm-testsuite for reasons that appear to be unknown or out of the compilers control. rdar://20803802 documents the investigation of these effects. While it is probably a good idea to perform the same switch for the other ARM out-of-order CPUs, I limited this change to swift as I cannot perform the benchmark verification on the other CPUs. Differential Revision: http://reviews.llvm.org/D10513 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242588 91177308-0d34-0410-b5e6-96231b3b80d8
97 lines
3.9 KiB
LLVM
97 lines
3.9 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=cortex-a9 -stress-ivchain | FileCheck %s
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; REQUIRES: asserts
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; @sharedidx is an unrolled variant of this loop:
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; for (unsigned long i = 0; i < len; i += s) {
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; c[i] = a[i] + b[i];
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; }
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; where 's' cannot be folded into the addressing mode.
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;
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; This is not quite profitable to chain. But with -stress-ivchain, we
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; can form three address chains in place of the shared induction
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; variable.
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; rdar://10674430
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define void @sharedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c, i32 %s, i32 %len) nounwind ssp {
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entry:
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; CHECK-LABEL: sharedidx:
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%cmp8 = icmp eq i32 %len, 0
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br i1 %cmp8, label %for.end, label %for.body
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for.body: ; preds = %entry, %for.body.3
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; CHECK: %for.body
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; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
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; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
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%i.09 = phi i32 [ %add5.3, %for.body.3 ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i8, i8* %a, i32 %i.09
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%0 = load i8, i8* %arrayidx, align 1
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%conv6 = zext i8 %0 to i32
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%arrayidx1 = getelementptr inbounds i8, i8* %b, i32 %i.09
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%1 = load i8, i8* %arrayidx1, align 1
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%conv27 = zext i8 %1 to i32
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%add = add nsw i32 %conv27, %conv6
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%conv3 = trunc i32 %add to i8
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%arrayidx4 = getelementptr inbounds i8, i8* %c, i32 %i.09
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store i8 %conv3, i8* %arrayidx4, align 1
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%add5 = add i32 %i.09, %s
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%cmp = icmp ult i32 %add5, %len
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br i1 %cmp, label %for.body.1, label %for.end
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for.end: ; preds = %for.body, %for.body.1, %for.body.2, %for.body.3, %entry
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ret void
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for.body.1: ; preds = %for.body
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; CHECK: %for.body.1
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; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
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; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
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%arrayidx.1 = getelementptr inbounds i8, i8* %a, i32 %add5
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%2 = load i8, i8* %arrayidx.1, align 1
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%conv6.1 = zext i8 %2 to i32
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%arrayidx1.1 = getelementptr inbounds i8, i8* %b, i32 %add5
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%3 = load i8, i8* %arrayidx1.1, align 1
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%conv27.1 = zext i8 %3 to i32
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%add.1 = add nsw i32 %conv27.1, %conv6.1
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%conv3.1 = trunc i32 %add.1 to i8
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%arrayidx4.1 = getelementptr inbounds i8, i8* %c, i32 %add5
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store i8 %conv3.1, i8* %arrayidx4.1, align 1
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%add5.1 = add i32 %add5, %s
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%cmp.1 = icmp ult i32 %add5.1, %len
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br i1 %cmp.1, label %for.body.2, label %for.end
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for.body.2: ; preds = %for.body.1
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; CHECK: %for.body.2
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; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
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; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
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%arrayidx.2 = getelementptr inbounds i8, i8* %a, i32 %add5.1
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%4 = load i8, i8* %arrayidx.2, align 1
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%conv6.2 = zext i8 %4 to i32
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%arrayidx1.2 = getelementptr inbounds i8, i8* %b, i32 %add5.1
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%5 = load i8, i8* %arrayidx1.2, align 1
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%conv27.2 = zext i8 %5 to i32
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%add.2 = add nsw i32 %conv27.2, %conv6.2
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%conv3.2 = trunc i32 %add.2 to i8
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%arrayidx4.2 = getelementptr inbounds i8, i8* %c, i32 %add5.1
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store i8 %conv3.2, i8* %arrayidx4.2, align 1
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%add5.2 = add i32 %add5.1, %s
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%cmp.2 = icmp ult i32 %add5.2, %len
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br i1 %cmp.2, label %for.body.3, label %for.end
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for.body.3: ; preds = %for.body.2
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; CHECK: %for.body.3
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; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
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; CHECK: ldrb {{r[0-9]+|lr}}, [{{r[0-9]+|lr}}, {{r[0-9]+|lr}}]!
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%arrayidx.3 = getelementptr inbounds i8, i8* %a, i32 %add5.2
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%6 = load i8, i8* %arrayidx.3, align 1
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%conv6.3 = zext i8 %6 to i32
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%arrayidx1.3 = getelementptr inbounds i8, i8* %b, i32 %add5.2
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%7 = load i8, i8* %arrayidx1.3, align 1
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%conv27.3 = zext i8 %7 to i32
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%add.3 = add nsw i32 %conv27.3, %conv6.3
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%conv3.3 = trunc i32 %add.3 to i8
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%arrayidx4.3 = getelementptr inbounds i8, i8* %c, i32 %add5.2
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store i8 %conv3.3, i8* %arrayidx4.3, align 1
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%add5.3 = add i32 %add5.2, %s
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%cmp.3 = icmp ult i32 %add5.3, %len
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br i1 %cmp.3, label %for.body, label %for.end
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}
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