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llvm-6502/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir
Alex Lorenz c225eda1f1 MIR Serialization: Serialize the floating point immediate machine operands.
Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243780 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 20:49:21 +00:00

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# RUN: not llc -march=nvptx -mcpu=sm_20 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
--- |
define float @test(float %k) {
entry:
%0 = fadd float %k, 3.250000e+00
ret float %0
}
...
---
name: test
registers:
- { id: 0, class: float32regs }
- { id: 1, class: float32regs }
body:
- id: 0
name: entry
instructions:
- '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'
# CHECK: [[@LINE+1]]:38: expected a floating point literal
- '%1 = FADD_rnf32ri %0, float 3'
- 'StoreRetvalF32 %1, 0'
- Return
...