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3ecdd44e5d
This patch adds support for v8i16 and v16i8 shuffle lowering using the immediate versions of the SSE4A EXTRQ and INSERTQ instructions. Although rather limited (they can only act on the lower 64-bits of the source vectors, leave the upper 64-bits of the result vector undefined and don't have VEX encoded variants), the instructions are still useful for the zero extension of any lane (EXTRQ) or inserting a lane into another vector (INSERTQ). Testing demonstrated that it wasn't typically worth it to use these instructions for v2i64 or v4i32 vector shuffles although they are capable of it. As well as adding specific pattern matching for the shuffles, the patch uses EXTRQ for zero extension cases where SSE41 isn't available and its more efficient than the SSE2 'unpack' default approach. It also adds shuffle decode support for the EXTRQ / INSERTQ cases when the instructions are handling full byte-sized extractions / insertions. From this foundation, future patches will be able to make use of the instructions for situations that use their ability to extract/insert at the bit level. Differential Revision: http://reviews.llvm.org/D10146 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241508 91177308-0d34-0410-b5e6-96231b3b80d8
114 lines
4.5 KiB
C++
114 lines
4.5 KiB
C++
//===-- X86ShuffleDecode.h - X86 shuffle decode logic -----------*-C++-*---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Define several functions to decode x86 specific shuffle semantics into a
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// generic vector mask.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_UTILS_X86SHUFFLEDECODE_H
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#define LLVM_LIB_TARGET_X86_UTILS_X86SHUFFLEDECODE_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/ArrayRef.h"
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//===----------------------------------------------------------------------===//
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// Vector Mask Decoding
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//===----------------------------------------------------------------------===//
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namespace llvm {
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class Constant;
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class MVT;
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enum { SM_SentinelUndef = -1, SM_SentinelZero = -2 };
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void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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// <3,1> or <6,7,2,3>
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void DecodeMOVHLPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask);
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// <0,2> or <0,1,4,5>
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void DecodeMOVLHPSMask(unsigned NElts, SmallVectorImpl<int> &ShuffleMask);
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void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
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void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
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void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
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void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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void DecodePSHUFLWMask(MVT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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/// DecodeSHUFPMask - This decodes the shuffle masks for shufp*. VT indicates
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/// the type of the vector allowing it to handle different datatypes and vector
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/// widths.
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void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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/// DecodeUNPCKHMask - This decodes the shuffle masks for unpckhps/unpckhpd
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/// and punpckh*. VT indicates the type of the vector allowing it to handle
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/// different datatypes and vector widths.
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void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
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/// DecodeUNPCKLMask - This decodes the shuffle masks for unpcklps/unpcklpd
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/// and punpckl*. VT indicates the type of the vector allowing it to handle
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/// different datatypes and vector widths.
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void DecodeUNPCKLMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
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/// \brief Decode a PSHUFB mask from an IR-level vector constant.
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void DecodePSHUFBMask(const Constant *C, SmallVectorImpl<int> &ShuffleMask);
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/// \brief Decode a PSHUFB mask from a raw array of constants such as from
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/// BUILD_VECTOR.
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void DecodePSHUFBMask(ArrayRef<uint64_t> RawMask,
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SmallVectorImpl<int> &ShuffleMask);
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/// \brief Decode a BLEND immediate mask into a shuffle mask.
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void DecodeBLENDMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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void DecodeVPERM2X128Mask(MVT VT, unsigned Imm,
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SmallVectorImpl<int> &ShuffleMask);
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/// DecodeVPERMMask - this decodes the shuffle masks for VPERMQ/VPERMPD.
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/// No VT provided since it only works on 256-bit, 4 element vectors.
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void DecodeVPERMMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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/// \brief Decode a VPERMILP variable mask from an IR-level vector constant.
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void DecodeVPERMILPMask(const Constant *C, SmallVectorImpl<int> &ShuffleMask);
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/// \brief Decode a zero extension instruction as a shuffle mask.
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void DecodeZeroExtendMask(MVT SrcVT, MVT DstVT,
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SmallVectorImpl<int> &ShuffleMask);
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/// \brief Decode a move lower and zero upper instruction as a shuffle mask.
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void DecodeZeroMoveLowMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
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/// \brief Decode a scalar float move instruction as a shuffle mask.
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void DecodeScalarMoveMask(MVT VT, bool IsLoad,
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SmallVectorImpl<int> &ShuffleMask);
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/// \brief Decode a SSE4A EXTRQ instruction as a v16i8 shuffle mask.
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void DecodeEXTRQIMask(int Len, int Idx,
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SmallVectorImpl<int> &ShuffleMask);
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/// \brief Decode a SSE4A INSERTQ instruction as a v16i8 shuffle mask.
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void DecodeINSERTQIMask(int Len, int Idx,
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SmallVectorImpl<int> &ShuffleMask);
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} // llvm namespace
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#endif
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