Vasileios Kalintiris 1a71ee21d3 [mips] Added support for the ERETNC instruction. ...

Summary: This required adding the instruction predicate HasMips32r5.

Patch by Scott Egerton.

Reviewers: dsanders, vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11136

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242666 91177308-0d34-0410-b5e6-96231b3b80d8

2015-07-20 12:28:56 +00:00

..

valid-mips32r6-el.txt

[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.

2015-06-27 15:39:19 +00:00

valid-mips32r6.txt

[mips] Added support for the ERETNC instruction.

2015-07-20 12:28:56 +00:00

valid-xfail-mips32r6.txt

[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.

2015-01-29 11:33:41 +00:00