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mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-20 11:32:33 +00:00
Evan Cheng 0104d9de04 - Assign load / store with shifter op address modes the right itinerary classes.
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 01:49:06 +00:00
2010-10-08 00:36:21 +00:00
2010-10-27 01:07:41 +00:00
2010-01-09 18:40:31 +00:00
2010-08-15 07:07:12 +00:00
2010-09-29 17:39:29 +00:00

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LLVM backend for 6502
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