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https://github.com/c64scene-ar/llvm-6502.git
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a21e2eae3d
instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127644 91177308-0d34-0410-b5e6-96231b3b80d8
560 lines
17 KiB
C++
560 lines
17 KiB
C++
//===- X86Disassembler.cpp - Disassembler for x86 and x86_64 ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the X86 Disassembler.
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// It contains code to translate the data produced by the decoder into
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// MCInsts.
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// Documentation for the disassembler can be found in X86Disassembler.h.
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//
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//===----------------------------------------------------------------------===//
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#include "X86Disassembler.h"
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#include "X86DisassemblerDecoder.h"
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#include "llvm/MC/EDInstInfo.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MemoryObject.h"
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#include "llvm/Support/raw_ostream.h"
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#include "X86GenRegisterNames.inc"
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#include "X86GenEDInfo.inc"
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using namespace llvm;
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using namespace llvm::X86Disassembler;
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void x86DisassemblerDebug(const char *file,
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unsigned line,
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const char *s) {
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dbgs() << file << ":" << line << ": " << s;
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}
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#define debug(s) DEBUG(x86DisassemblerDebug(__FILE__, __LINE__, s));
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namespace llvm {
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// Fill-ins to make the compiler happy. These constants are never actually
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// assigned; they are just filler to make an automatically-generated switch
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// statement work.
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namespace X86 {
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enum {
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BX_SI = 500,
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BX_DI = 501,
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BP_SI = 502,
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BP_DI = 503,
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sib = 504,
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sib64 = 505
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};
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}
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extern Target TheX86_32Target, TheX86_64Target;
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}
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static bool translateInstruction(MCInst &target,
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InternalInstruction &source);
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X86GenericDisassembler::X86GenericDisassembler(DisassemblerMode mode) :
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MCDisassembler(),
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fMode(mode) {
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}
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X86GenericDisassembler::~X86GenericDisassembler() {
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}
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EDInstInfo *X86GenericDisassembler::getEDInfo() const {
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return instInfoX86;
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}
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/// regionReader - a callback function that wraps the readByte method from
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/// MemoryObject.
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///
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/// @param arg - The generic callback parameter. In this case, this should
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/// be a pointer to a MemoryObject.
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/// @param byte - A pointer to the byte to be read.
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/// @param address - The address to be read.
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static int regionReader(void* arg, uint8_t* byte, uint64_t address) {
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MemoryObject* region = static_cast<MemoryObject*>(arg);
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return region->readByte(address, byte);
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}
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/// logger - a callback function that wraps the operator<< method from
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/// raw_ostream.
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///
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/// @param arg - The generic callback parameter. This should be a pointe
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/// to a raw_ostream.
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/// @param log - A string to be logged. logger() adds a newline.
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static void logger(void* arg, const char* log) {
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if (!arg)
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return;
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raw_ostream &vStream = *(static_cast<raw_ostream*>(arg));
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vStream << log << "\n";
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}
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//
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// Public interface for the disassembler
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//
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bool X86GenericDisassembler::getInstruction(MCInst &instr,
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uint64_t &size,
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const MemoryObject ®ion,
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uint64_t address,
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raw_ostream &vStream) const {
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InternalInstruction internalInstr;
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int ret = decodeInstruction(&internalInstr,
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regionReader,
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(void*)®ion,
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logger,
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(void*)&vStream,
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address,
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fMode);
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if (ret) {
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size = internalInstr.readerCursor - address;
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return false;
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}
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else {
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size = internalInstr.length;
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return !translateInstruction(instr, internalInstr);
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}
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}
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//
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// Private code that translates from struct InternalInstructions to MCInsts.
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//
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/// translateRegister - Translates an internal register to the appropriate LLVM
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/// register, and appends it as an operand to an MCInst.
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///
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/// @param mcInst - The MCInst to append to.
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/// @param reg - The Reg to append.
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static void translateRegister(MCInst &mcInst, Reg reg) {
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#define ENTRY(x) X86::x,
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uint8_t llvmRegnums[] = {
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ALL_REGS
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0
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};
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#undef ENTRY
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uint8_t llvmRegnum = llvmRegnums[reg];
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mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
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}
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/// translateImmediate - Appends an immediate operand to an MCInst.
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///
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/// @param mcInst - The MCInst to append to.
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/// @param immediate - The immediate value to append.
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/// @param operand - The operand, as stored in the descriptor table.
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/// @param insn - The internal instruction.
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static void translateImmediate(MCInst &mcInst, uint64_t immediate,
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const OperandSpecifier &operand,
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InternalInstruction &insn) {
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// Sign-extend the immediate if necessary.
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OperandType type = operand.type;
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if (type == TYPE_RELv) {
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switch (insn.displacementSize) {
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default:
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break;
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case 1:
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type = TYPE_MOFFS8;
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break;
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case 2:
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type = TYPE_MOFFS16;
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break;
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case 4:
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type = TYPE_MOFFS32;
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break;
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case 8:
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type = TYPE_MOFFS64;
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break;
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}
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}
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switch (type) {
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case TYPE_MOFFS8:
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case TYPE_REL8:
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if(immediate & 0x80)
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immediate |= ~(0xffull);
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break;
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case TYPE_MOFFS16:
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if(immediate & 0x8000)
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immediate |= ~(0xffffull);
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break;
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case TYPE_MOFFS32:
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case TYPE_REL32:
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case TYPE_REL64:
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if(immediate & 0x80000000)
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immediate |= ~(0xffffffffull);
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break;
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case TYPE_MOFFS64:
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default:
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// operand is 64 bits wide. Do nothing.
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break;
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}
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mcInst.addOperand(MCOperand::CreateImm(immediate));
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}
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/// translateRMRegister - Translates a register stored in the R/M field of the
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/// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
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/// @param mcInst - The MCInst to append to.
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/// @param insn - The internal instruction to extract the R/M field
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/// from.
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/// @return - 0 on success; -1 otherwise
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static bool translateRMRegister(MCInst &mcInst,
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InternalInstruction &insn) {
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if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
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debug("A R/M register operand may not have a SIB byte");
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return true;
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}
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switch (insn.eaBase) {
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default:
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debug("Unexpected EA base register");
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return true;
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case EA_BASE_NONE:
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debug("EA_BASE_NONE for ModR/M base");
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return true;
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#define ENTRY(x) case EA_BASE_##x:
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ALL_EA_BASES
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#undef ENTRY
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debug("A R/M register operand may not have a base; "
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"the operand must be a register.");
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return true;
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#define ENTRY(x) \
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case EA_REG_##x: \
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mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
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ALL_REGS
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#undef ENTRY
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}
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return false;
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}
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/// translateRMMemory - Translates a memory operand stored in the Mod and R/M
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/// fields of an internal instruction (and possibly its SIB byte) to a memory
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/// operand in LLVM's format, and appends it to an MCInst.
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///
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/// @param mcInst - The MCInst to append to.
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/// @param insn - The instruction to extract Mod, R/M, and SIB fields
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/// from.
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/// @return - 0 on success; nonzero otherwise
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static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn) {
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// Addresses in an MCInst are represented as five operands:
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// 1. basereg (register) The R/M base, or (if there is a SIB) the
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// SIB base
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// 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
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// scale amount
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// 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
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// the index (which is multiplied by the
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// scale amount)
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// 4. displacement (immediate) 0, or the displacement if there is one
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// 5. segmentreg (register) x86_registerNONE for now, but could be set
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// if we have segment overrides
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MCOperand baseReg;
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MCOperand scaleAmount;
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MCOperand indexReg;
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MCOperand displacement;
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MCOperand segmentReg;
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if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
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if (insn.sibBase != SIB_BASE_NONE) {
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switch (insn.sibBase) {
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default:
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debug("Unexpected sibBase");
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return true;
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#define ENTRY(x) \
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case SIB_BASE_##x: \
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baseReg = MCOperand::CreateReg(X86::x); break;
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ALL_SIB_BASES
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#undef ENTRY
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}
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} else {
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baseReg = MCOperand::CreateReg(0);
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}
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if (insn.sibIndex != SIB_INDEX_NONE) {
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switch (insn.sibIndex) {
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default:
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debug("Unexpected sibIndex");
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return true;
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#define ENTRY(x) \
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case SIB_INDEX_##x: \
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indexReg = MCOperand::CreateReg(X86::x); break;
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EA_BASES_32BIT
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EA_BASES_64BIT
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#undef ENTRY
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}
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} else {
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indexReg = MCOperand::CreateReg(0);
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}
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scaleAmount = MCOperand::CreateImm(insn.sibScale);
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} else {
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switch (insn.eaBase) {
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case EA_BASE_NONE:
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if (insn.eaDisplacement == EA_DISP_NONE) {
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debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
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return true;
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}
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if (insn.mode == MODE_64BIT)
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baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
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else
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baseReg = MCOperand::CreateReg(0);
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indexReg = MCOperand::CreateReg(0);
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break;
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case EA_BASE_BX_SI:
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baseReg = MCOperand::CreateReg(X86::BX);
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indexReg = MCOperand::CreateReg(X86::SI);
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break;
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case EA_BASE_BX_DI:
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baseReg = MCOperand::CreateReg(X86::BX);
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indexReg = MCOperand::CreateReg(X86::DI);
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break;
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case EA_BASE_BP_SI:
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baseReg = MCOperand::CreateReg(X86::BP);
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indexReg = MCOperand::CreateReg(X86::SI);
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break;
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case EA_BASE_BP_DI:
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baseReg = MCOperand::CreateReg(X86::BP);
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indexReg = MCOperand::CreateReg(X86::DI);
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break;
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default:
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indexReg = MCOperand::CreateReg(0);
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switch (insn.eaBase) {
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default:
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debug("Unexpected eaBase");
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return true;
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// Here, we will use the fill-ins defined above. However,
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// BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
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// sib and sib64 were handled in the top-level if, so they're only
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// placeholders to keep the compiler happy.
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#define ENTRY(x) \
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case EA_BASE_##x: \
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baseReg = MCOperand::CreateReg(X86::x); break;
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ALL_EA_BASES
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#undef ENTRY
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#define ENTRY(x) case EA_REG_##x:
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ALL_REGS
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#undef ENTRY
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debug("A R/M memory operand may not be a register; "
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"the base field must be a base.");
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return true;
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}
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}
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scaleAmount = MCOperand::CreateImm(1);
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}
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displacement = MCOperand::CreateImm(insn.displacement);
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static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
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0, // SEG_OVERRIDE_NONE
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X86::CS,
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X86::SS,
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X86::DS,
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X86::ES,
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X86::FS,
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X86::GS
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};
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segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
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mcInst.addOperand(baseReg);
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mcInst.addOperand(scaleAmount);
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mcInst.addOperand(indexReg);
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mcInst.addOperand(displacement);
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mcInst.addOperand(segmentReg);
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return false;
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}
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/// translateRM - Translates an operand stored in the R/M (and possibly SIB)
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/// byte of an instruction to LLVM form, and appends it to an MCInst.
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///
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/// @param mcInst - The MCInst to append to.
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/// @param operand - The operand, as stored in the descriptor table.
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/// @param insn - The instruction to extract Mod, R/M, and SIB fields
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/// from.
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/// @return - 0 on success; nonzero otherwise
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static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
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InternalInstruction &insn) {
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switch (operand.type) {
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default:
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debug("Unexpected type for a R/M operand");
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return true;
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case TYPE_R8:
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case TYPE_R16:
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case TYPE_R32:
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case TYPE_R64:
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case TYPE_Rv:
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case TYPE_MM:
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case TYPE_MM32:
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case TYPE_MM64:
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case TYPE_XMM:
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case TYPE_XMM32:
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case TYPE_XMM64:
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case TYPE_XMM128:
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case TYPE_XMM256:
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case TYPE_DEBUGREG:
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case TYPE_CONTROLREG:
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return translateRMRegister(mcInst, insn);
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case TYPE_M:
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case TYPE_M8:
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case TYPE_M16:
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case TYPE_M32:
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case TYPE_M64:
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case TYPE_M128:
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case TYPE_M256:
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case TYPE_M512:
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case TYPE_Mv:
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case TYPE_M32FP:
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case TYPE_M64FP:
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case TYPE_M80FP:
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case TYPE_M16INT:
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case TYPE_M32INT:
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case TYPE_M64INT:
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case TYPE_M1616:
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case TYPE_M1632:
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case TYPE_M1664:
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case TYPE_LEA:
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return translateRMMemory(mcInst, insn);
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}
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}
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/// translateFPRegister - Translates a stack position on the FPU stack to its
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/// LLVM form, and appends it to an MCInst.
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///
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/// @param mcInst - The MCInst to append to.
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/// @param stackPos - The stack position to translate.
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/// @return - 0 on success; nonzero otherwise.
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static bool translateFPRegister(MCInst &mcInst,
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uint8_t stackPos) {
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if (stackPos >= 8) {
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debug("Invalid FP stack position");
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return true;
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}
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mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
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return false;
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}
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/// translateOperand - Translates an operand stored in an internal instruction
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/// to LLVM's format and appends it to an MCInst.
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///
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/// @param mcInst - The MCInst to append to.
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/// @param operand - The operand, as stored in the descriptor table.
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/// @param insn - The internal instruction.
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/// @return - false on success; true otherwise.
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static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
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InternalInstruction &insn) {
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switch (operand.encoding) {
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default:
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debug("Unhandled operand encoding during translation");
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return true;
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case ENCODING_REG:
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translateRegister(mcInst, insn.reg);
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return false;
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case ENCODING_RM:
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return translateRM(mcInst, operand, insn);
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case ENCODING_CB:
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case ENCODING_CW:
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case ENCODING_CD:
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case ENCODING_CP:
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case ENCODING_CO:
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case ENCODING_CT:
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debug("Translation of code offsets isn't supported.");
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return true;
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case ENCODING_IB:
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case ENCODING_IW:
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case ENCODING_ID:
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case ENCODING_IO:
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case ENCODING_Iv:
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case ENCODING_Ia:
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translateImmediate(mcInst,
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insn.immediates[insn.numImmediatesTranslated++],
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operand,
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insn);
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return false;
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case ENCODING_RB:
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case ENCODING_RW:
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case ENCODING_RD:
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case ENCODING_RO:
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translateRegister(mcInst, insn.opcodeRegister);
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return false;
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case ENCODING_I:
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return translateFPRegister(mcInst, insn.opcodeModifier);
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case ENCODING_Rv:
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translateRegister(mcInst, insn.opcodeRegister);
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return false;
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case ENCODING_VVVV:
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translateRegister(mcInst, insn.vvvv);
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return false;
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case ENCODING_DUP:
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return translateOperand(mcInst,
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insn.spec->operands[operand.type - TYPE_DUP0],
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insn);
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}
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}
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/// translateInstruction - Translates an internal instruction and all its
|
|
/// operands to an MCInst.
|
|
///
|
|
/// @param mcInst - The MCInst to populate with the instruction's data.
|
|
/// @param insn - The internal instruction.
|
|
/// @return - false on success; true otherwise.
|
|
static bool translateInstruction(MCInst &mcInst,
|
|
InternalInstruction &insn) {
|
|
if (!insn.spec) {
|
|
debug("Instruction has no specification");
|
|
return true;
|
|
}
|
|
|
|
mcInst.setOpcode(insn.instructionID);
|
|
|
|
int index;
|
|
|
|
insn.numImmediatesTranslated = 0;
|
|
|
|
for (index = 0; index < X86_MAX_OPERANDS; ++index) {
|
|
if (insn.spec->operands[index].encoding != ENCODING_NONE) {
|
|
if (translateOperand(mcInst, insn.spec->operands[index], insn)) {
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static MCDisassembler *createX86_32Disassembler(const Target &T) {
|
|
return new X86Disassembler::X86_32Disassembler;
|
|
}
|
|
|
|
static MCDisassembler *createX86_64Disassembler(const Target &T) {
|
|
return new X86Disassembler::X86_64Disassembler;
|
|
}
|
|
|
|
extern "C" void LLVMInitializeX86Disassembler() {
|
|
// Register the disassembler.
|
|
TargetRegistry::RegisterMCDisassembler(TheX86_32Target,
|
|
createX86_32Disassembler);
|
|
TargetRegistry::RegisterMCDisassembler(TheX86_64Target,
|
|
createX86_64Disassembler);
|
|
}
|