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https://github.com/c64scene-ar/llvm-6502.git
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59ee62d241
and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
78 lines
2.6 KiB
C++
78 lines
2.6 KiB
C++
//===- MBlazeSubtarget.cpp - MBlaze Subtarget Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the MBlaze specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "MBlazeSubtarget.h"
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#include "MBlaze.h"
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#include "MBlazeRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetRegistry.h"
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#define GET_SUBTARGETINFO_ENUM
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#define GET_SUBTARGETINFO_MC_DESC
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "MBlazeGenSubtargetInfo.inc"
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using namespace llvm;
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MBlazeSubtarget::MBlazeSubtarget(const std::string &TT,
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const std::string &CPU,
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const std::string &FS):
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MBlazeGenSubtargetInfo(TT, CPU, FS),
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HasBarrel(false), HasDiv(false), HasMul(false), HasPatCmp(false),
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HasFPU(false), HasMul64(false), HasSqrt(false)
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{
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// Parse features string.
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std::string CPUName = CPU;
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if (CPUName.empty())
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CPUName = "mblaze";
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ParseSubtargetFeatures(CPUName, FS);
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// Only use instruction scheduling if the selected CPU has an instruction
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// itinerary (the default CPU is the only one that doesn't).
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HasItin = CPUName != "mblaze";
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DEBUG(dbgs() << "CPU " << CPUName << "(" << HasItin << ")\n");
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUName);
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// Compute the issue width of the MBlaze itineraries
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computeIssueWidth();
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}
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void MBlazeSubtarget::computeIssueWidth() {
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InstrItins.IssueWidth = 1;
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}
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bool MBlazeSubtarget::
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enablePostRAScheduler(CodeGenOpt::Level OptLevel,
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TargetSubtargetInfo::AntiDepBreakMode& Mode,
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RegClassVector& CriticalPathRCs) const {
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Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
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CriticalPathRCs.clear();
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CriticalPathRCs.push_back(&MBlaze::GPRRegClass);
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return HasItin && OptLevel >= CodeGenOpt::Default;
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}
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MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU,
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StringRef FS) {
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MCSubtargetInfo *X = new MCSubtargetInfo();
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InitMBlazeMCSubtargetInfo(X, TT, CPU, FS);
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return X;
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}
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extern "C" void LLVMInitializeMBlazeMCSubtargetInfo() {
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TargetRegistry::RegisterMCSubtargetInfo(TheMBlazeTarget,
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createMBlazeMCSubtargetInfo);
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}
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