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https://github.com/c64scene-ar/llvm-6502.git
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43d225dc8b
We default to inserting to lane 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105722 91177308-0d34-0410-b5e6-96231b3b80d8
132 lines
4.3 KiB
LLVM
132 lines
4.3 KiB
LLVM
; RUN: llc < %s -march=cellspu > %t1.s
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; RUN: grep cbd %t1.s | count 5
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; RUN: grep chd %t1.s | count 5
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; RUN: grep cwd %t1.s | count 11
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; RUN: grep -w il %t1.s | count 5
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; RUN: grep -w ilh %t1.s | count 6
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; RUN: grep iohl %t1.s | count 1
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; RUN: grep ilhu %t1.s | count 4
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; RUN: grep shufb %t1.s | count 27
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; RUN: grep 17219 %t1.s | count 1
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; RUN: grep 22598 %t1.s | count 1
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; RUN: grep -- -39 %t1.s | count 1
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; RUN: grep 24 %t1.s | count 1
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; RUN: grep 1159 %t1.s | count 1
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; RUN: FileCheck %s < %t1.s
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; ModuleID = 'vecinsert.bc'
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
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target triple = "spu-unknown-elf"
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; 67 -> 0x43, as 8-bit vector constant load = 0x4343 (17219)0x4343
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define <16 x i8> @test_v16i8(<16 x i8> %P, i8 %x) {
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entry:
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%tmp1 = insertelement <16 x i8> %P, i8 %x, i32 10
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%tmp1.1 = insertelement <16 x i8> %tmp1, i8 67, i32 7
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%tmp1.2 = insertelement <16 x i8> %tmp1.1, i8 %x, i32 15
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ret <16 x i8> %tmp1.2
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}
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; 22598 -> 0x5846
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define <8 x i16> @test_v8i16(<8 x i16> %P, i16 %x) {
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entry:
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%tmp1 = insertelement <8 x i16> %P, i16 %x, i32 5
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%tmp1.1 = insertelement <8 x i16> %tmp1, i16 22598, i32 7
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%tmp1.2 = insertelement <8 x i16> %tmp1.1, i16 %x, i32 2
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ret <8 x i16> %tmp1.2
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}
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; 1574023 -> 0x180487 (ILHU 24/IOHL 1159)
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define <4 x i32> @test_v4i32_1(<4 x i32> %P, i32 %x) {
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entry:
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%tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2
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%tmp1.1 = insertelement <4 x i32> %tmp1, i32 1574023, i32 1
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%tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3
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ret <4 x i32> %tmp1.2
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}
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; Should generate IL for the load
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define <4 x i32> @test_v4i32_2(<4 x i32> %P, i32 %x) {
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entry:
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%tmp1 = insertelement <4 x i32> %P, i32 %x, i32 2
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%tmp1.1 = insertelement <4 x i32> %tmp1, i32 -39, i32 1
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%tmp1.2 = insertelement <4 x i32> %tmp1.1, i32 %x, i32 3
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ret <4 x i32> %tmp1.2
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}
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define void @variable_v16i8_1(<16 x i8>* %a, i32 %i) nounwind {
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entry:
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%arrayidx = getelementptr <16 x i8>* %a, i32 %i
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%tmp2 = load <16 x i8>* %arrayidx
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%tmp3 = insertelement <16 x i8> %tmp2, i8 1, i32 1
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%tmp8 = insertelement <16 x i8> %tmp3, i8 2, i32 11
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store <16 x i8> %tmp8, <16 x i8>* %arrayidx
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ret void
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}
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define void @variable_v8i16_1(<8 x i16>* %a, i32 %i) nounwind {
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entry:
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%arrayidx = getelementptr <8 x i16>* %a, i32 %i
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%tmp2 = load <8 x i16>* %arrayidx
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%tmp3 = insertelement <8 x i16> %tmp2, i16 1, i32 1
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%tmp8 = insertelement <8 x i16> %tmp3, i16 2, i32 6
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store <8 x i16> %tmp8, <8 x i16>* %arrayidx
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ret void
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}
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define void @variable_v4i32_1(<4 x i32>* %a, i32 %i) nounwind {
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entry:
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%arrayidx = getelementptr <4 x i32>* %a, i32 %i
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%tmp2 = load <4 x i32>* %arrayidx
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%tmp3 = insertelement <4 x i32> %tmp2, i32 1, i32 1
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%tmp8 = insertelement <4 x i32> %tmp3, i32 2, i32 2
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store <4 x i32> %tmp8, <4 x i32>* %arrayidx
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ret void
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}
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define void @variable_v4f32_1(<4 x float>* %a, i32 %i) nounwind {
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entry:
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%arrayidx = getelementptr <4 x float>* %a, i32 %i
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%tmp2 = load <4 x float>* %arrayidx
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%tmp3 = insertelement <4 x float> %tmp2, float 1.000000e+00, i32 1
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%tmp8 = insertelement <4 x float> %tmp3, float 2.000000e+00, i32 2
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store <4 x float> %tmp8, <4 x float>* %arrayidx
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ret void
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}
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define void @variable_v2i64_1(<2 x i64>* %a, i32 %i) nounwind {
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entry:
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%arrayidx = getelementptr <2 x i64>* %a, i32 %i
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%tmp2 = load <2 x i64>* %arrayidx
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%tmp3 = insertelement <2 x i64> %tmp2, i64 615, i32 0
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store <2 x i64> %tmp3, <2 x i64>* %arrayidx
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ret void
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}
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define void @variable_v2i64_2(<2 x i64>* %a, i32 %i) nounwind {
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entry:
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%arrayidx = getelementptr <2 x i64>* %a, i32 %i
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%tmp2 = load <2 x i64>* %arrayidx
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%tmp3 = insertelement <2 x i64> %tmp2, i64 615, i32 1
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store <2 x i64> %tmp3, <2 x i64>* %arrayidx
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ret void
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}
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define void @variable_v2f64_1(<2 x double>* %a, i32 %i) nounwind {
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entry:
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%arrayidx = getelementptr <2 x double>* %a, i32 %i
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%tmp2 = load <2 x double>* %arrayidx
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%tmp3 = insertelement <2 x double> %tmp2, double 1.000000e+00, i32 1
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store <2 x double> %tmp3, <2 x double>* %arrayidx
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ret void
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}
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define <4 x i32> @undef_v4i32( i32 %param ) {
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;CHECK: cwd
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;CHECK: lqa
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;CHECK: shufb
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%val = insertelement <4 x i32> <i32 1, i32 2, i32 3, i32 4>, i32 %param, i32 undef
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ret <4 x i32> %val
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}
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