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https://github.com/c64scene-ar/llvm-6502.git
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605c40341b
We used to only combine intrinsics, and turn them into VLD1_UPD/VST1_UPD when the base pointer is incremented after the load/store. We can do the same thing for generic load/stores. Note that we can only combine the first load/store+adds pair in a sequence (as might be generated for a v16f32 load for instance), because other combines turn the base pointer addition chain (each computing the address of the next load, from the address of the last load) into independent additions (common base pointer + this load's offset). Differential Revision: http://reviews.llvm.org/D6585 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223862 91177308-0d34-0410-b5e6-96231b3b80d8
185 lines
5.3 KiB
LLVM
185 lines
5.3 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
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target triple = "thumbv7s-apple-ios8.0.0"
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define <8 x i8> @load_v8i8(<8 x i8>** %ptr) {
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;CHECK-LABEL: load_v8i8:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <8 x i8>** %ptr
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%lA = load <8 x i8>* %A, align 1
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ret <8 x i8> %lA
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}
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define <8 x i8> @load_v8i8_update(<8 x i8>** %ptr) {
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;CHECK-LABEL: load_v8i8_update:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <8 x i8>** %ptr
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%lA = load <8 x i8>* %A, align 1
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%inc = getelementptr <8 x i8>* %A, i38 1
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store <8 x i8>* %inc, <8 x i8>** %ptr
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ret <8 x i8> %lA
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}
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define <4 x i16> @load_v4i16(<4 x i16>** %ptr) {
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;CHECK-LABEL: load_v4i16:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <4 x i16>** %ptr
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%lA = load <4 x i16>* %A, align 1
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ret <4 x i16> %lA
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}
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define <4 x i16> @load_v4i16_update(<4 x i16>** %ptr) {
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;CHECK-LABEL: load_v4i16_update:
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;CHECK: vld1.16 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <4 x i16>** %ptr
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%lA = load <4 x i16>* %A, align 1
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%inc = getelementptr <4 x i16>* %A, i34 1
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store <4 x i16>* %inc, <4 x i16>** %ptr
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ret <4 x i16> %lA
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}
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define <2 x i32> @load_v2i32(<2 x i32>** %ptr) {
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;CHECK-LABEL: load_v2i32:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <2 x i32>** %ptr
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%lA = load <2 x i32>* %A, align 1
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ret <2 x i32> %lA
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}
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define <2 x i32> @load_v2i32_update(<2 x i32>** %ptr) {
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;CHECK-LABEL: load_v2i32_update:
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;CHECK: vld1.32 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x i32>** %ptr
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%lA = load <2 x i32>* %A, align 1
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%inc = getelementptr <2 x i32>* %A, i32 1
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store <2 x i32>* %inc, <2 x i32>** %ptr
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ret <2 x i32> %lA
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}
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define <2 x float> @load_v2f32(<2 x float>** %ptr) {
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;CHECK-LABEL: load_v2f32:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <2 x float>** %ptr
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%lA = load <2 x float>* %A, align 1
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ret <2 x float> %lA
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}
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define <2 x float> @load_v2f32_update(<2 x float>** %ptr) {
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;CHECK-LABEL: load_v2f32_update:
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;CHECK: vld1.32 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x float>** %ptr
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%lA = load <2 x float>* %A, align 1
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%inc = getelementptr <2 x float>* %A, i32 1
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store <2 x float>* %inc, <2 x float>** %ptr
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ret <2 x float> %lA
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}
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define <1 x i64> @load_v1i64(<1 x i64>** %ptr) {
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;CHECK-LABEL: load_v1i64:
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;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <1 x i64>** %ptr
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%lA = load <1 x i64>* %A, align 1
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ret <1 x i64> %lA
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}
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define <1 x i64> @load_v1i64_update(<1 x i64>** %ptr) {
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;CHECK-LABEL: load_v1i64_update:
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;CHECK: vld1.64 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <1 x i64>** %ptr
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%lA = load <1 x i64>* %A, align 1
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%inc = getelementptr <1 x i64>* %A, i31 1
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store <1 x i64>* %inc, <1 x i64>** %ptr
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ret <1 x i64> %lA
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}
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define <16 x i8> @load_v16i8(<16 x i8>** %ptr) {
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;CHECK-LABEL: load_v16i8:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <16 x i8>** %ptr
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%lA = load <16 x i8>* %A, align 1
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ret <16 x i8> %lA
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}
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define <16 x i8> @load_v16i8_update(<16 x i8>** %ptr) {
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;CHECK-LABEL: load_v16i8_update:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <16 x i8>** %ptr
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%lA = load <16 x i8>* %A, align 1
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%inc = getelementptr <16 x i8>* %A, i316 1
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store <16 x i8>* %inc, <16 x i8>** %ptr
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ret <16 x i8> %lA
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}
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define <8 x i16> @load_v8i16(<8 x i16>** %ptr) {
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;CHECK-LABEL: load_v8i16:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <8 x i16>** %ptr
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%lA = load <8 x i16>* %A, align 1
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ret <8 x i16> %lA
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}
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define <8 x i16> @load_v8i16_update(<8 x i16>** %ptr) {
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;CHECK-LABEL: load_v8i16_update:
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;CHECK: vld1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <8 x i16>** %ptr
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%lA = load <8 x i16>* %A, align 1
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%inc = getelementptr <8 x i16>* %A, i38 1
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store <8 x i16>* %inc, <8 x i16>** %ptr
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ret <8 x i16> %lA
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}
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define <4 x i32> @load_v4i32(<4 x i32>** %ptr) {
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;CHECK-LABEL: load_v4i32:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <4 x i32>** %ptr
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%lA = load <4 x i32>* %A, align 1
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ret <4 x i32> %lA
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}
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define <4 x i32> @load_v4i32_update(<4 x i32>** %ptr) {
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;CHECK-LABEL: load_v4i32_update:
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;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <4 x i32>** %ptr
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%lA = load <4 x i32>* %A, align 1
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%inc = getelementptr <4 x i32>* %A, i34 1
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store <4 x i32>* %inc, <4 x i32>** %ptr
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ret <4 x i32> %lA
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}
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define <4 x float> @load_v4f32(<4 x float>** %ptr) {
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;CHECK-LABEL: load_v4f32:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <4 x float>** %ptr
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%lA = load <4 x float>* %A, align 1
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ret <4 x float> %lA
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}
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define <4 x float> @load_v4f32_update(<4 x float>** %ptr) {
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;CHECK-LABEL: load_v4f32_update:
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;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <4 x float>** %ptr
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%lA = load <4 x float>* %A, align 1
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%inc = getelementptr <4 x float>* %A, i34 1
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store <4 x float>* %inc, <4 x float>** %ptr
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ret <4 x float> %lA
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}
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define <2 x i64> @load_v2i64(<2 x i64>** %ptr) {
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;CHECK-LABEL: load_v2i64:
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;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
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%A = load <2 x i64>** %ptr
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%lA = load <2 x i64>* %A, align 1
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ret <2 x i64> %lA
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}
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define <2 x i64> @load_v2i64_update(<2 x i64>** %ptr) {
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;CHECK-LABEL: load_v2i64_update:
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;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
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%A = load <2 x i64>** %ptr
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%lA = load <2 x i64>* %A, align 1
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%inc = getelementptr <2 x i64>* %A, i32 1
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store <2 x i64>* %inc, <2 x i64>** %ptr
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ret <2 x i64> %lA
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}
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