Benjamin Kramer 17c836c4b5 X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures. ... * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transfer the comparison result from FPSW into EFLAGS. If you're wondering about the right-shift: That's an implicit sub-register extraction (%ax -> %ah) which is handled later on by the instruction selector. Fixes PR6679. Patch by Christoph Erhardt! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8		2012-04-27 12:07:43 +00:00
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ARM	Implement a bastardized ABI.	2012-04-27 02:11:10 +00:00
CellSPU
CPP
Generic
Hexagon	Revert r155365, r155366, and r155367. All three of these have regression	2012-04-23 18:25:57 +00:00
MBlaze
Mips	Do not use $gp as a dedicated global register if the target ABI is not O32.	2012-04-25 01:24:52 +00:00
MSP430
PowerPC
PTX
SPARC
Thumb	- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2	2012-04-27 01:27:19 +00:00
Thumb2	If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume	2012-04-26 01:13:36 +00:00
X86	X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures.	2012-04-27 12:07:43 +00:00
XCore