llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-13 10:32:06 +00:00

History

Benjamin Kramer 17c836c4b5 X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures.

* Model FPSW (the FPU status word) as a register.
* Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions.
* During Legalize/Lowering, build a node sequence to transfer the comparison
result from FPSW into EFLAGS. If you're wondering about the right-shift: That's
an implicit sub-register extraction (%ax -> %ah) which is handled later on by
the instruction selector.

Fixes PR6679. Patch by Christoph Erhardt!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8

2012-04-27 12:07:43 +00:00

ARM

Implement a bastardized ABI.

2012-04-27 02:11:10 +00:00

CellSPU

Flip the new block-placement pass to be on by default.

2012-04-16 13:49:17 +00:00

CPP

…

Generic

Move to X86 directory because this fails on non-X86 platforms.

2012-04-16 16:38:48 +00:00