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https://github.com/c64scene-ar/llvm-6502.git
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b3f912b510
r186399 aggressively used the RISBG instruction for immediate ANDs, both because it can handle some values that AND IMMEDIATE can't, and because it allows the destination register to be different from the source. I realized later while implementing the distinct-ops support that it would be better to leave the choice up to convertToThreeAddress() instead. The AND IMMEDIATE form is shorter and is less likely to be cracked. This is a problem for 32-bit ANDs because we assume that all 32-bit operations will leave the high word untouched, whereas RISBG used in this way will either clear the high word or copy it from the source register. The patch uses the z196 instruction RISBLG for this instead. This means that z10 will be restricted to NILL, NILH and NILF for 32-bit ANDs, but I think that should be OK for now. Although we're using z10 as the base architecture, the optimization work is going to be focused more on z196 and zEC12. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187492 91177308-0d34-0410-b5e6-96231b3b80d8
227 lines
6.6 KiB
LLVM
227 lines
6.6 KiB
LLVM
; Test 8-bit atomic min/max operations.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2
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; Check signed minimum.
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; - CHECK is for the main loop.
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; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
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; RLL is set up correctly. The negation is independent of the NILL and L
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; tested in CHECK.
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; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
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; before being used, and that the low bits are set to 1. This sequence is
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; independent of the other loop prologue instructions.
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define i16 @f1(i16 *%src, i16 %b) {
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; CHECK-LABEL: f1:
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; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK: nill %r2, 65532
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; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
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; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]]
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; CHECK: risbg [[ROT]], %r3, 32, 47, 0
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; CHECK: [[KEEP]]:
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
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; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
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; CHECK: jlh [[LOOP]]
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; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f1:
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; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: br %r14
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;
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; CHECK-SHIFT2-LABEL: f1:
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; CHECK-SHIFT2: sll %r3, 16
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: crjle {{%r[0-9]+}}, %r3
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw min i16 *%src, i16 %b seq_cst
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ret i16 %res
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}
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; Check signed maximum.
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define i16 @f2(i16 *%src, i16 %b) {
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; CHECK-LABEL: f2:
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; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK: nill %r2, 65532
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; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
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; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]]
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; CHECK: risbg [[ROT]], %r3, 32, 47, 0
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; CHECK: [[KEEP]]:
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
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; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
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; CHECK: jlh [[LOOP]]
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; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f2:
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; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: br %r14
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;
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; CHECK-SHIFT2-LABEL: f2:
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; CHECK-SHIFT2: sll %r3, 16
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: crjhe {{%r[0-9]+}}, %r3
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw max i16 *%src, i16 %b seq_cst
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ret i16 %res
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}
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; Check unsigned minimum.
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define i16 @f3(i16 *%src, i16 %b) {
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; CHECK-LABEL: f3:
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; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK: nill %r2, 65532
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; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
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; CHECK: clr [[ROT]], %r3
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; CHECK: jle [[KEEP:\..*]]
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; CHECK: risbg [[ROT]], %r3, 32, 47, 0
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; CHECK: [[KEEP]]:
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
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; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
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; CHECK: jlh [[LOOP]]
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; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f3:
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; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: br %r14
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;
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; CHECK-SHIFT2-LABEL: f3:
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; CHECK-SHIFT2: sll %r3, 16
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw umin i16 *%src, i16 %b seq_cst
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ret i16 %res
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}
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; Check unsigned maximum.
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define i16 @f4(i16 *%src, i16 %b) {
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; CHECK-LABEL: f4:
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; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK: nill %r2, 65532
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; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
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; CHECK: [[LOOP:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
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; CHECK: clr [[ROT]], %r3
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; CHECK: jhe [[KEEP:\..*]]
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; CHECK: risbg [[ROT]], %r3, 32, 47, 0
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; CHECK: [[KEEP]]:
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
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; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
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; CHECK: jlh [[LOOP]]
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; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f4:
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; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT1: rll
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; CHECK-SHIFT1: br %r14
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;
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; CHECK-SHIFT2-LABEL: f4:
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; CHECK-SHIFT2: sll %r3, 16
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: rll
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw umax i16 *%src, i16 %b seq_cst
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ret i16 %res
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}
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; Check the lowest useful signed minimum value. We need to load 0x80010000
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; into the source register.
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define i16 @f5(i16 *%src) {
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; CHECK-LABEL: f5:
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; CHECK: llilh [[SRC2:%r[0-9]+]], 32769
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; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
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; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f5:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2-LABEL: f5:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw min i16 *%src, i16 -32767 seq_cst
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ret i16 %res
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}
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; Check the highest useful signed maximum value. We need to load 0x7ffe0000
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; into the source register.
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define i16 @f6(i16 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: llilh [[SRC2:%r[0-9]+]], 32766
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; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
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; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f6:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2-LABEL: f6:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw max i16 *%src, i16 32766 seq_cst
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ret i16 %res
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}
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; Check the lowest useful unsigned maximum value. We need to load 0x00010000
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; into the source register.
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define i16 @f7(i16 *%src) {
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; CHECK-LABEL: f7:
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; CHECK: llilh [[SRC2:%r[0-9]+]], 1
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; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
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; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f7:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2-LABEL: f7:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw umin i16 *%src, i16 1 seq_cst
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ret i16 %res
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}
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; Check the highest useful unsigned maximum value. We need to load 0xfffe0000
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; into the source register.
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define i16 @f8(i16 *%src) {
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; CHECK-LABEL: f8:
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; CHECK: llilh [[SRC2:%r[0-9]+]], 65534
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; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
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; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
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; CHECK: br %r14
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;
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; CHECK-SHIFT1-LABEL: f8:
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; CHECK-SHIFT1: br %r14
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; CHECK-SHIFT2-LABEL: f8:
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; CHECK-SHIFT2: br %r14
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%res = atomicrmw umax i16 *%src, i16 65534 seq_cst
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ret i16 %res
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}
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