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https://github.com/c64scene-ar/llvm-6502.git
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04c559569f
The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193179 91177308-0d34-0410-b5e6-96231b3b80d8
375 lines
12 KiB
C++
375 lines
12 KiB
C++
//===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI Implementation of TargetInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "SIInstrInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "SIDefines.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCInstrDesc.h"
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using namespace llvm;
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SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
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: AMDGPUInstrInfo(tm),
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RI(tm)
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{ }
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const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const {
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return RI;
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}
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void
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SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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// If we are trying to copy to or from SCC, there is a bug somewhere else in
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// the backend. While it may be theoretically possible to do this, it should
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// never be necessary.
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assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
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static const int16_t Sub0_15[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
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AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
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AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
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AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
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};
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static const int16_t Sub0_7[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
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AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
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};
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static const int16_t Sub0_3[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
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};
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static const int16_t Sub0_2[] = {
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AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
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};
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static const int16_t Sub0_1[] = {
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AMDGPU::sub0, AMDGPU::sub1, 0
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};
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unsigned Opcode;
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const int16_t *SubIndices;
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if (AMDGPU::M0 == DestReg) {
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// Check if M0 isn't already set to this value
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for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
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I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
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if (!I->definesRegister(AMDGPU::M0))
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continue;
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unsigned Opc = I->getOpcode();
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if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
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break;
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if (!I->readsRegister(SrcReg))
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break;
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// The copy isn't necessary
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return;
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}
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}
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if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
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BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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} else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
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BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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} else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
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Opcode = AMDGPU::S_MOV_B32;
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SubIndices = Sub0_3;
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} else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
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Opcode = AMDGPU::S_MOV_B32;
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SubIndices = Sub0_7;
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} else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
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Opcode = AMDGPU::S_MOV_B32;
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SubIndices = Sub0_15;
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} else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
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AMDGPU::SReg_32RegClass.contains(SrcReg));
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BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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return;
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} else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
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AMDGPU::SReg_64RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_1;
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} else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_2;
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} else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
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AMDGPU::SReg_128RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_3;
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} else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
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AMDGPU::SReg_256RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_7;
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} else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
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AMDGPU::SReg_512RegClass.contains(SrcReg));
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Opcode = AMDGPU::V_MOV_B32_e32;
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SubIndices = Sub0_15;
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} else {
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llvm_unreachable("Can't copy register!");
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}
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while (unsigned SubIdx = *SubIndices++) {
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MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
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get(Opcode), RI.getSubReg(DestReg, SubIdx));
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Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
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if (*SubIndices)
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Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
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}
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}
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unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
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int NewOpc;
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// Try to map original to commuted opcode
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if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
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return NewOpc;
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// Try to map commuted to original opcode
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if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
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return NewOpc;
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return Opcode;
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}
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MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
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bool NewMI) const {
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if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg() ||
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!MI->getOperand(2).isReg())
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return 0;
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MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
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if (MI)
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MI->setDesc(get(commuteOpcode(MI->getOpcode())));
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return MI;
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}
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MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg,
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unsigned SrcReg) const {
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assert(!"Not Implemented");
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}
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bool SIInstrInfo::isMov(unsigned Opcode) const {
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switch(Opcode) {
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default: return false;
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case AMDGPU::S_MOV_B32:
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case AMDGPU::S_MOV_B64:
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case AMDGPU::V_MOV_B32_e32:
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case AMDGPU::V_MOV_B32_e64:
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return true;
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}
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}
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bool
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SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
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return RC != &AMDGPU::EXECRegRegClass;
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}
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int SIInstrInfo::isMIMG(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::MIMG;
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}
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int SIInstrInfo::isSMRD(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SMRD;
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}
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bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP1;
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}
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bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP2;
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}
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bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP3;
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}
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bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOPC;
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}
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bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
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if(MO.isImm()) {
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return MO.getImm() >= -16 && MO.getImm() <= 64;
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}
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if (MO.isFPImm()) {
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return MO.getFPImm()->isExactlyValue(0.0) ||
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MO.getFPImm()->isExactlyValue(0.5) ||
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MO.getFPImm()->isExactlyValue(-0.5) ||
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MO.getFPImm()->isExactlyValue(1.0) ||
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MO.getFPImm()->isExactlyValue(-1.0) ||
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MO.getFPImm()->isExactlyValue(2.0) ||
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MO.getFPImm()->isExactlyValue(-2.0) ||
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MO.getFPImm()->isExactlyValue(4.0) ||
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MO.getFPImm()->isExactlyValue(-4.0);
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}
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return false;
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}
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bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
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return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
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}
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bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
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StringRef &ErrInfo) const {
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uint16_t Opcode = MI->getOpcode();
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int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
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int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
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int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
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// Verify VOP*
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if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
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unsigned ConstantBusCount = 0;
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unsigned SGPRUsed = AMDGPU::NoRegister;
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for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isUse() &&
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!TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
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// EXEC register uses the constant bus.
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if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
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++ConstantBusCount;
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// SGPRs use the constant bus
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if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
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(!MO.isImplicit() &&
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(AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
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AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
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if (SGPRUsed != MO.getReg()) {
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++ConstantBusCount;
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SGPRUsed = MO.getReg();
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}
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}
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}
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// Literal constants use the constant bus.
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if (isLiteralConstant(MO))
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++ConstantBusCount;
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}
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if (ConstantBusCount > 1) {
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ErrInfo = "VOP* instruction uses the constant bus more than once";
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return false;
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}
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}
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// Verify SRC1 for VOP2 and VOPC
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if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
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const MachineOperand &Src1 = MI->getOperand(Src1Idx);
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if (Src1.isImm()) {
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ErrInfo = "VOP[2C] src1 cannot be an immediate.";
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return false;
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}
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}
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// Verify VOP3
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if (isVOP3(Opcode)) {
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if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
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ErrInfo = "VOP3 src0 cannot be a literal constant.";
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return false;
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}
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if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
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ErrInfo = "VOP3 src1 cannot be a literal constant.";
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return false;
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}
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if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
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ErrInfo = "VOP3 src2 cannot be a literal constant.";
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return false;
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}
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}
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return true;
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}
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//===----------------------------------------------------------------------===//
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// Indirect addressing callbacks
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//===----------------------------------------------------------------------===//
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unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
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unsigned Channel) const {
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assert(Channel == 0);
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return RegIndex;
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}
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int SIInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
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llvm_unreachable("Unimplemented");
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}
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int SIInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
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llvm_unreachable("Unimplemented");
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}
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const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
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llvm_unreachable("Unimplemented");
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}
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MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address, unsigned OffsetReg) const {
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llvm_unreachable("Unimplemented");
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}
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MachineInstrBuilder SIInstrInfo::buildIndirectRead(
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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unsigned ValueReg,
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unsigned Address, unsigned OffsetReg) const {
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llvm_unreachable("Unimplemented");
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}
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