Matt Arsenault 054f4eccd2 R600: Fix trunc store from i64 to i1 ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203695 91177308-0d34-0410-b5e6-96231b3b80d8

2014-03-12 18:45:52 +00:00

..

AArch64

IR: add a second ordering operand to cmpxhg for failure

2014-03-11 10:48:52 +00:00

ARM

ARM: correct Dwarf output for non-contiguous VFP saves.

2014-03-12 11:29:23 +00:00

CPP

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Generic

CommandLine: Exit successfully for -version and -help

2014-02-28 19:08:01 +00:00

Hexagon

Fix broken CHECK lines

2014-02-16 07:31:05 +00:00

Inputs

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Mips

[mips] BSEL's and BINS[RL] operands are reversed compared to the vselect node used in the pattern.

2014-03-12 11:54:00 +00:00

MSP430

Fix known typos

2014-01-24 17:20:08 +00:00

NVPTX

Followup to r203483 - add test.

2014-03-10 20:36:04 +00:00

PowerPC

IR: add a second ordering operand to cmpxhg for failure

2014-03-11 10:48:52 +00:00

R600

R600: Fix trunc store from i64 to i1

2014-03-12 18:45:52 +00:00

SPARC

IR: add a second ordering operand to cmpxhg for failure

2014-03-11 10:48:52 +00:00

SystemZ

IR: add a second ordering operand to cmpxhg for failure

2014-03-11 10:48:52 +00:00

Thumb

Add triples to try to fix the windows bots.

2014-02-13 16:49:47 +00:00

Thumb2

ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block

2014-02-26 11:27:28 +00:00

X86

X86: Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059)

2014-03-11 15:49:24 +00:00

XCore

[XCore] Add support for the "m" inline asm constraint.

2014-03-06 16:37:48 +00:00