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llvm-6502/lib/Target/Sparc
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Brian Gaeke fbe558c993 pseudocode for 64-bit lshr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18154 91177308-0d34-0410-b5e6-96231b3b80d8
2004-11-23 08:14:09 +00:00
..
DelaySlotFiller.cpp
Use TargetMachine::hasDelaySlot() instead of our old switch statement
2004-09-30 04:04:47 +00:00
FPMover.cpp
Pass which converts FpMOVD (double move pseudoinstructions) to pairs
2004-09-29 03:24:34 +00:00
Makefile
Change name of target lib to conform to new naming scheme.
2004-10-29 21:57:16 +00:00
README.txt
Add more known-failing tests.
2004-11-23 06:39:50 +00:00
Sparc.h
Add createSparcV8FPMoverPass().
2004-09-29 03:25:39 +00:00
Sparc.td
Prettify formatting of the file, adjust paths to making V8 a subdir of Sparc
2004-09-22 20:09:29 +00:00
SparcAsmPrinter.cpp
Handle GhostLinkage case for completeness (should not be seen by the asm writer)
2004-11-19 21:49:19 +00:00
SparcInstrFormats.td
Class F2_1 already inherits the imm22 field from class F2
2004-10-14 22:32:24 +00:00
SparcInstrInfo.cpp
Recognize FpMOVD as a move.
2004-09-29 16:45:47 +00:00
SparcInstrInfo.h
I think that V8 should coallesce registers, don't you?
2004-07-25 06:19:04 +00:00
SparcInstrInfo.td
Add the rest of the logical instructions.
2004-11-23 06:39:37 +00:00
SparcRegisterInfo.cpp
Remove dependency on MRegisterInfo::getRegClass
2004-10-29 21:42:27 +00:00
SparcRegisterInfo.h
Code insertion methods now return void instead of an int.
2004-08-15 22:15:11 +00:00
SparcRegisterInfo.td
Allocate fewer registers and tighten up alignment restrictions.
2004-11-18 00:25:20 +00:00
SparcTargetMachine.cpp
Allocate fewer registers and tighten up alignment restrictions.
2004-11-18 00:25:20 +00:00
SparcTargetMachine.h
Implement getModuleMatchQuality and getJITMatchQuality so that v8 will be the
2004-10-09 05:57:01 +00:00
SparcV8CodeEmitter.cpp
* Add baseline structural JIT code, but disable the JIT to allow llvm-gcc builds
2004-10-19 19:49:42 +00:00
SparcV8ISelSimple.cpp
pseudocode for 64-bit lshr.
2004-11-23 08:14:09 +00:00
SparcV8JITInfo.h
SparcV8 skeleton
2004-02-25 19:28:19 +00:00

README.txt 

SparcV8 backend skeleton
------------------------

This directory houses a 32-bit SPARC V8 backend employing an expander-based
instruction selector.  It is not yet functionally complete.  Watch
this space for more news coming soon!

Current expected test failures
------------------------------

All SingleSource/Benchmarks tests are expected to pass.  Currently, all
C++ tests are expected to fail.  Here are the known SingleSource failures:

	UnitTests/SetjmpLongjmp/C++/C++Catch
	UnitTests/SetjmpLongjmp/C++/SimpleC++Test
	Regression/C++/EH/ConditionalExpr
	Regression/C++/EH/ctor_dtor_count-2
	Regression/C++/EH/ctor_dtor_count
	Regression/C++/EH/exception_spec_test
	Regression/C++/EH/function_try_block
	Regression/C++/EH/simple_rethrow
	Regression/C++/EH/simple_throw
	Regression/C++/EH/throw_rethrow_test
	CustomChecked/oopack_v1p8

Here are some known MultiSource test failures - this is probably not a
complete list right now.

	burg siod lambda make_dparser hbd treecc hexxagon fhourstones
	bisect testtrie eks imp bh power anagram bc distray

To-do
-----

* support shifts on longs
* support casting 64-bit integers to FP types
* support FP rem

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