Jim Laskey 063e765345 Adding basic support for Dwarf line number debug information. ...

I promise to keep future commits smaller.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25396 91177308-0d34-0410-b5e6-96231b3b80d8

2006-01-17 17:31:53 +00:00

..

Alpha

fix short immediate loads

2006-01-16 21:41:39 +00:00

CBackend

yet more C++ standards-compliance stuff.

2005-12-27 10:40:34 +00:00

IA64

oops, this shouldn't have gotten in

2006-01-17 03:09:48 +00:00

PowerPC

Adding basic support for Dwarf line number debug information.

2006-01-17 17:31:53 +00:00

Skeleton

Support multiple ValueTypes per RegisterClass, needed for upcoming vector

2005-12-01 04:51:06 +00:00

Sparc

Silly Sparc is big endian. If we have to load args out of incoming stack slots

2006-01-16 01:40:00 +00:00

SparcV8

Silly Sparc is big endian. If we have to load args out of incoming stack slots

2006-01-16 01:40:00 +00:00

SparcV9

Support multiple ValueTypes per RegisterClass, needed for upcoming vector

2005-12-01 04:51:06 +00:00

X86

Zero extending load from i1 to i8.

2006-01-17 07:02:46 +00:00

Makefile

DONT_BUILD_RELINKED is gone and implied by BUILD_ARCHIVE now

2005-10-24 02:26:13 +00:00

MRegisterInfo.cpp

Rename MRegisterDesc -> TargetRegisterDesc for consistency

2005-09-30 17:49:27 +00:00

SubtargetFeature.cpp

Preparation of supporting scheduling info. Need to find info based on selected

2005-10-25 15:15:28 +00:00

Target.td

New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace

2006-01-09 18:28:21 +00:00

TargetData.cpp

Implement a new InvalidateStructLayoutInfo method and add some comments

2006-01-14 00:07:34 +00:00

TargetFrameInfo.cpp

…

TargetInstrInfo.cpp

…

TargetMachine.cpp

…

TargetMachineRegistry.cpp

…

TargetSchedInfo.cpp

…

TargetSchedule.td

add a marker

2005-10-23 22:07:20 +00:00

TargetSelectionDAG.td

bswap implementation

2006-01-14 03:14:10 +00:00

TargetSubtarget.cpp

…