Jim Laskey 076866c50f Checking in first round of scheduling tablegen files. Not tied in as yet. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23786 91177308-0d34-0410-b5e6-96231b3b80d8

2005-10-18 16:23:40 +00:00

..

Alpha

This seems useful from the original patch that added the function. If there is a reason it is not useful on a RISC type target, let me know and I will pull it out

2005-10-09 20:11:35 +00:00

CBackend

fix CBackend/2005-09-27-VolatileFuncPtr.ll

2005-09-27 20:52:44 +00:00

IA64

Fix CodeGen/Generic/bool-to-double.ll

2005-10-07 04:50:48 +00:00

PowerPC

Checking in first round of scheduling tablegen files. Not tied in as yet.

2005-10-18 16:23:40 +00:00

Skeleton

CR registers are not used by this "target"

2005-09-30 06:43:58 +00:00

Sparc

silence some warnings

2005-10-05 17:15:09 +00:00

SparcV8

silence some warnings

2005-10-05 17:15:09 +00:00

SparcV9

silence a warning

2005-10-02 16:27:59 +00:00

X86

Remove some dead code now that the dag combiner exists.

2005-10-15 22:08:02 +00:00

Makefile

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MRegisterInfo.cpp

Rename MRegisterDesc -> TargetRegisterDesc for consistency

2005-09-30 17:49:27 +00:00

SubtargetFeature.cpp

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Target.td

Pull DAG ISel generation nodes out of the PowerPC backend to where they

2005-10-10 06:00:30 +00:00

TargetData.cpp

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TargetFrameInfo.cpp

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TargetInstrInfo.cpp

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TargetMachine.cpp

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TargetMachineRegistry.cpp

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TargetSchedInfo.cpp

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TargetSchedule.td

Checking in first round of scheduling tablegen files. Not tied in as yet.

2005-10-18 16:23:40 +00:00

TargetSelectionDAG.td

add the integer truncate/extension operations

2005-10-14 06:40:20 +00:00

TargetSubtarget.cpp

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