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https://github.com/c64scene-ar/llvm-6502.git
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15b2838035
of FMOVS instrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16570 91177308-0d34-0410-b5e6-96231b3b80d8
92 lines
3.4 KiB
C++
92 lines
3.4 KiB
C++
//===-- FPMover.cpp - SparcV8 double-precision floating point move fixer --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Turns FpMOVD instructions into FMOVS pairs after regalloc.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV8.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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namespace {
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Statistic<> NumFpMOVDs ("fpmover", "# FpMOVD instructions translated");
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struct FPMover : public MachineFunctionPass {
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/// Target machine description which we query for reg. names, data
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/// layout, etc.
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///
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TargetMachine &TM;
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FPMover (TargetMachine &tm) : TM (tm) { }
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virtual const char *getPassName () const {
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return "SparcV8 Double-FP Move Fixer";
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}
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bool runOnMachineBasicBlock (MachineBasicBlock &MBB);
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bool runOnMachineFunction (MachineFunction &F) {
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bool Changed = false;
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for (MachineFunction::iterator FI = F.begin (), FE = F.end ();
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FI != FE; ++FI)
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Changed |= runOnMachineBasicBlock (*FI);
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return Changed;
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}
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};
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} // end of anonymous namespace
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/// createSparcV8FPMoverPass - Returns a pass that turns FpMOVD
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/// instructions into FMOVS instructions
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///
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FunctionPass *llvm::createSparcV8FPMoverPass (TargetMachine &tm) {
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return new FPMover (tm);
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}
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static void doubleToSingleRegPair(unsigned doubleReg, unsigned &singleReg1, unsigned &singleReg2) {
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const unsigned EvenHalvesOfPairs[] = { V8::F0, V8::F2, V8::F4, V8::F6, V8::F8, V8::F10, V8::F12, V8::F14, V8::F16, V8::F18, V8::F20, V8::F22, V8::F24, V8::F26, V8::F28, V8::F30 };
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const unsigned OddHalvesOfPairs[] = { V8::F1, V8::F3, V8::F5, V8::F7, V8::F9, V8::F11, V8::F13, V8::F15, V8::F17, V8::F19, V8::F21, V8::F23, V8::F25, V8::F27, V8::F29, V8::F31 };
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const unsigned DoubleRegsInOrder[] = { V8::D0, V8::D1, V8::D2, V8::D3, V8::D4, V8::D5, V8::D6, V8::D7, V8::D8, V8::D9, V8::D10, V8::D11, V8::D12, V8::D13, V8::D14, V8::D15 };
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for (unsigned i = 0; i < sizeof(DoubleRegsInOrder)/sizeof(unsigned); ++i)
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if (DoubleRegsInOrder[i] == doubleReg) {
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singleReg1 = EvenHalvesOfPairs[i];
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singleReg2 = OddHalvesOfPairs[i];
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return;
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}
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assert (0 && "Can't find reg");
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}
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/// runOnMachineBasicBlock - Fixup FpMOVD instructions in this MBB.
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///
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bool FPMover::runOnMachineBasicBlock (MachineBasicBlock &MBB) {
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bool Changed = false;
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for (MachineBasicBlock::iterator I = MBB.begin (); I != MBB.end (); ++I)
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if (V8::FpMOVD == I->getOpcode()) {
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I->setOpcode (V8::FMOVS);
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unsigned DestReg = I->getOperand(0).getReg();
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unsigned SrcReg = I->getOperand(1).getReg();
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unsigned NewSrcReg0, NewSrcReg1;
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unsigned NewDestReg0, NewDestReg1;
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doubleToSingleRegPair (DestReg, NewDestReg0, NewDestReg1);
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doubleToSingleRegPair (SrcReg, NewSrcReg0, NewSrcReg1);
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I->SetMachineOperandReg (0, NewDestReg0);
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I->SetMachineOperandReg (1, NewSrcReg0);
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// Insert copy for the other half of the double:
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MachineBasicBlock::iterator J = I;
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++J;
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BuildMI (MBB, J, V8::FMOVS, 1, NewDestReg1).addReg(NewSrcReg1);
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++NumFpMOVDs;
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Changed = true;
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}
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return Changed;
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}
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