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https://github.com/c64scene-ar/llvm-6502.git
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083b48af14
It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162061 91177308-0d34-0410-b5e6-96231b3b80d8
40 lines
992 B
LLVM
40 lines
992 B
LLVM
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
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define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK: t1
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; CHECK: mvn r0, #-2147483648
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; CHECK: cmp r2, #10
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; CHECK: it le
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; CHECK: addle.w r1, r1, r0
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; CHECK: mov r0, r1
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%tmp1 = icmp sgt i32 %c, 10
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%tmp2 = select i1 %tmp1, i32 0, i32 2147483647
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%tmp3 = add i32 %tmp2, %b
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ret i32 %tmp3
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}
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define i32 @t2(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK: t2
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; CHECK: cmp r2, #10
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; CHECK: it le
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; CHECK: addle.w r1, r1, #-2147483648
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; CHECK: mov r0, r1
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%tmp1 = icmp sgt i32 %c, 10
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%tmp2 = select i1 %tmp1, i32 0, i32 2147483648
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%tmp3 = add i32 %tmp2, %b
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ret i32 %tmp3
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}
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define i32 @t3(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; CHECK: t3
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; CHECK: cmp r2, #10
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; CHECK: it le
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; CHECK: suble.w r1, r1, #10
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; CHECK: mov r0, r1
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%tmp1 = icmp sgt i32 %c, 10
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%tmp2 = select i1 %tmp1, i32 0, i32 10
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%tmp3 = sub i32 %b, %tmp2
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ret i32 %tmp3
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}
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