llvm-6502

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History

Chandler Carruth 0889d65fd5 [x86] Make the previous logic significantly less conservative and get

a bunch more improvements.

Non-lane-crossing is fine, the key is that lane merging only makes sense
for single-input shuffles. Not sure why I got so turned around here. The
code all works, I was just using the wrong model for it.

This only updates v4 and v8 lowering. The v16 and v32 lowering requires
restructuring the entire check sequence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222537 91177308-0d34-0410-b5e6-96231b3b80d8

2014-11-21 14:33:24 +00:00

AArch64

DAGCombiner: Allow the DAGCombiner to combine multiple FDIVs with the same divisor info FMULs by the reciprocal.

2014-11-21 06:39:58 +00:00

ARM

Fix ARM triple parsing

2014-11-17 14:08:57 +00:00

CPP

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Generic

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Hexagon