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			96 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			TableGen
		
	
	
	
	
	
			
		
		
	
	
			96 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			TableGen
		
	
	
	
	
	
| //===- SparcV8InstrFormats.td - SparcV8 Instr Formats ------*- tablegen -*-===//
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| // 
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| //                     The LLVM Compiler Infrastructure
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| //
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| // This file was developed by the LLVM research group and is distributed under
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| // the University of Illinois Open Source License. See LICENSE.TXT for details.
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| // 
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| //===----------------------------------------------------------------------===//
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| 
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| //===----------------------------------------------------------------------===//
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| // Format #2 instruction classes in the SparcV8
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| //===----------------------------------------------------------------------===//
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| 
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| class F2 : InstV8 {                   // Format 2 instructions
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|   bits<3>  op2;
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|   bits<22> imm22;
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|   let op          = 0;    // op = 0
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|   let Inst{24-22} = op2;
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|   let Inst{21-0}  = imm22;
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| }
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| 
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| // Specific F2 classes: SparcV8 manual, page 44
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| //
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| class F2_1<bits<3> op2Val, string name> : F2 {
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|   bits<5>  rd;
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| 
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|   let op2         = op2Val;
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|   let Name        = name;
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| 
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|   let Inst{29-25} = rd;
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| }
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| 
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| class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
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|   bits<4>   cond;
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|   bit       annul = 0;     // currently unused
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| 
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|   let cond        = condVal;
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|   let op2         = op2Val;
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|   let Name        = name;
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| 
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|   let Inst{29}    = annul;
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|   let Inst{28-25} = cond;
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| }
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| 
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| //===----------------------------------------------------------------------===//
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| // Format #3 instruction classes in the SparcV8
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| //===----------------------------------------------------------------------===//
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| 
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| class F3 : InstV8 {
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|   bits<5> rd;
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|   bits<6> op3;
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|   bits<5> rs1;
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|   let op{1} = 1;   // Op = 2 or 3
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|   let Inst{29-25} = rd;
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|   let Inst{24-19} = op3;
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|   let Inst{18-14} = rs1;
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| }
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| 
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| // Specific F3 classes: SparcV8 manual, page 44
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| //
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| class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3 {
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|   bits<8> asi = 0; // asi not currently used in SparcV8
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|   bits<5> rs2;
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| 
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|   let op         = opVal;
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|   let op3        = op3val;
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|   let Name       = name;
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| 
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|   let Inst{13}   = 0;     // i field = 0
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|   let Inst{12-5} = asi;   // address space identifier
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|   let Inst{4-0}  = rs2;
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| }
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| 
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| class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3 {
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|   bits<13> simm13;
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| 
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|   let op         = opVal;
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|   let op3        = op3val;
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|   let Name       = name;
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| 
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|   let Inst{13}   = 1;     // i field = 1
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|   let Inst{12-0} = simm13;
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| }
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| 
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| // floating-point
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| class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, string name> : F3 {
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|   bits<5> rs2;
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| 
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|   let op         = opVal;
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|   let op3        = op3val;
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|   let Name       = name;
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| 
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|   let Inst{13-5} = opfval;   // fp opcode
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|   let Inst{4-0}  = rs2;
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| }
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