Nate Begeman 0976122abc Add support patterns to many load and store instructions which will ...

hopefully use patterns in the near future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24651 91177308-0d34-0410-b5e6-96231b3b80d8

2005-12-09 23:54:18 +00:00

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Alpha

it helps if your conditionals are not reversed

2005-12-09 00:45:42 +00:00

CBackend

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IA64

Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.

2005-12-05 02:34:29 +00:00

PowerPC

Add support patterns to many load and store instructions which will

2005-12-09 23:54:18 +00:00

Skeleton

Support multiple ValueTypes per RegisterClass, needed for upcoming vector

2005-12-01 04:51:06 +00:00

Sparc

Support multiple ValueTypes per RegisterClass, needed for upcoming vector

2005-12-01 04:51:06 +00:00

SparcV8

Support multiple ValueTypes per RegisterClass, needed for upcoming vector

2005-12-01 04:51:06 +00:00

SparcV9

Support multiple ValueTypes per RegisterClass, needed for upcoming vector

2005-12-01 04:51:06 +00:00

X86

Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al

2005-12-09 22:48:48 +00:00

Makefile

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MRegisterInfo.cpp

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SubtargetFeature.cpp

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Target.td

* Added instruction property hasCtrlDep for those which r/w control-flow

2005-12-04 08:13:17 +00:00

TargetData.cpp

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TargetFrameInfo.cpp

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TargetInstrInfo.cpp

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TargetMachine.cpp

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TargetMachineRegistry.cpp

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TargetSchedInfo.cpp

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TargetSchedule.td

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TargetSelectionDAG.td

Add SDTCisPtrTy and use it for loads, to indicate that the operand of a load

2005-12-09 22:58:42 +00:00

TargetSubtarget.cpp

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