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https://github.com/c64scene-ar/llvm-6502.git
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1d7153976c
Add a new test, and_ops_more.ll, which is XFAIL'd, to record the parts of and_ops.ll that were affected by this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50379 91177308-0d34-0410-b5e6-96231b3b80d8
280 lines
8.0 KiB
LLVM
280 lines
8.0 KiB
LLVM
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep and %t1.s | count 234
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; RUN: grep andc %t1.s | count 85
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; RUN: grep andi %t1.s | count 37
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; RUN: grep andhi %t1.s | count 30
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; RUN: grep andbi %t1.s | count 4
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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target triple = "spu"
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; AND instruction generation:
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define <4 x i32> @and_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
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%A = and <4 x i32> %arg1, %arg2
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ret <4 x i32> %A
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}
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define <4 x i32> @and_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
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%A = and <4 x i32> %arg2, %arg1
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ret <4 x i32> %A
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}
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define <8 x i16> @and_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
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%A = and <8 x i16> %arg1, %arg2
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ret <8 x i16> %A
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}
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define <8 x i16> @and_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
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%A = and <8 x i16> %arg2, %arg1
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ret <8 x i16> %A
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}
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define <16 x i8> @and_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
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%A = and <16 x i8> %arg2, %arg1
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ret <16 x i8> %A
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}
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define <16 x i8> @and_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
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%A = and <16 x i8> %arg1, %arg2
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ret <16 x i8> %A
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}
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define i32 @and_i32_1(i32 %arg1, i32 %arg2) {
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%A = and i32 %arg2, %arg1
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ret i32 %A
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}
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define i32 @and_i32_2(i32 %arg1, i32 %arg2) {
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%A = and i32 %arg1, %arg2
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ret i32 %A
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}
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define i16 @and_i16_1(i16 %arg1, i16 %arg2) {
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%A = and i16 %arg2, %arg1
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ret i16 %A
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}
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define i16 @and_i16_2(i16 %arg1, i16 %arg2) {
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%A = and i16 %arg1, %arg2
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ret i16 %A
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}
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define i8 @and_i8_1(i8 %arg1, i8 %arg2) {
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%A = and i8 %arg2, %arg1
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ret i8 %A
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}
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define i8 @and_i8_2(i8 %arg1, i8 %arg2) {
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%A = and i8 %arg1, %arg2
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ret i8 %A
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}
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; ANDC instruction generation:
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define <4 x i32> @andc_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) {
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%A = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 >
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%B = and <4 x i32> %arg1, %A
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ret <4 x i32> %B
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}
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define <4 x i32> @andc_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) {
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%A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
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%B = and <4 x i32> %arg2, %A
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ret <4 x i32> %B
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}
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define <4 x i32> @andc_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2) {
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%A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 >
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%B = and <4 x i32> %A, %arg2
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ret <4 x i32> %B
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}
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define <8 x i16> @andc_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) {
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%A = xor <8 x i16> %arg2, < i16 -1, i16 -1, i16 -1, i16 -1,
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i16 -1, i16 -1, i16 -1, i16 -1 >
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%B = and <8 x i16> %arg1, %A
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ret <8 x i16> %B
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}
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define <8 x i16> @andc_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) {
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%A = xor <8 x i16> %arg1, < i16 -1, i16 -1, i16 -1, i16 -1,
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i16 -1, i16 -1, i16 -1, i16 -1 >
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%B = and <8 x i16> %arg2, %A
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ret <8 x i16> %B
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}
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define <16 x i8> @andc_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) {
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%A = xor <16 x i8> %arg1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
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i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
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i8 -1, i8 -1, i8 -1, i8 -1 >
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%B = and <16 x i8> %arg2, %A
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ret <16 x i8> %B
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}
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define <16 x i8> @andc_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) {
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%A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
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i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
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i8 -1, i8 -1, i8 -1, i8 -1 >
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%B = and <16 x i8> %arg1, %A
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ret <16 x i8> %B
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}
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define <16 x i8> @andc_v16i8_3(<16 x i8> %arg1, <16 x i8> %arg2) {
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%A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
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i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1,
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i8 -1, i8 -1, i8 -1, i8 -1 >
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%B = and <16 x i8> %A, %arg1
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ret <16 x i8> %B
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}
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define i32 @andc_i32_1(i32 %arg1, i32 %arg2) {
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%A = xor i32 %arg2, -1
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%B = and i32 %A, %arg1
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ret i32 %B
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}
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define i32 @andc_i32_2(i32 %arg1, i32 %arg2) {
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%A = xor i32 %arg1, -1
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%B = and i32 %A, %arg2
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ret i32 %B
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}
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define i32 @andc_i32_3(i32 %arg1, i32 %arg2) {
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%A = xor i32 %arg2, -1
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%B = and i32 %arg1, %A
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ret i32 %B
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}
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define i16 @andc_i16_1(i16 %arg1, i16 %arg2) {
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%A = xor i16 %arg2, -1
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%B = and i16 %A, %arg1
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ret i16 %B
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}
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define i16 @andc_i16_2(i16 %arg1, i16 %arg2) {
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%A = xor i16 %arg1, -1
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%B = and i16 %A, %arg2
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ret i16 %B
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}
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define i16 @andc_i16_3(i16 %arg1, i16 %arg2) {
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%A = xor i16 %arg2, -1
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%B = and i16 %arg1, %A
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ret i16 %B
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}
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define i8 @andc_i8_1(i8 %arg1, i8 %arg2) {
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%A = xor i8 %arg2, -1
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%B = and i8 %A, %arg1
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ret i8 %B
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}
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define i8 @andc_i8_2(i8 %arg1, i8 %arg2) {
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%A = xor i8 %arg1, -1
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%B = and i8 %A, %arg2
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ret i8 %B
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}
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define i8 @andc_i8_3(i8 %arg1, i8 %arg2) {
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%A = xor i8 %arg2, -1
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%B = and i8 %arg1, %A
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ret i8 %B
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}
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; ANDI instruction generation (i32 data type):
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define <4 x i32> @andi_v4i32_1(<4 x i32> %in) {
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%tmp2 = and <4 x i32> %in, < i32 511, i32 511, i32 511, i32 511 >
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ret <4 x i32> %tmp2
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}
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define <4 x i32> @andi_v4i32_2(<4 x i32> %in) {
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%tmp2 = and <4 x i32> %in, < i32 510, i32 510, i32 510, i32 510 >
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ret <4 x i32> %tmp2
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}
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define <4 x i32> @andi_v4i32_3(<4 x i32> %in) {
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%tmp2 = and <4 x i32> %in, < i32 -1, i32 -1, i32 -1, i32 -1 >
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ret <4 x i32> %tmp2
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}
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define <4 x i32> @andi_v4i32_4(<4 x i32> %in) {
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%tmp2 = and <4 x i32> %in, < i32 -512, i32 -512, i32 -512, i32 -512 >
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ret <4 x i32> %tmp2
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}
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define i32 @andi_u32(i32 zeroext %in) zeroext {
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%tmp37 = and i32 %in, 37
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ret i32 %tmp37
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}
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define i32 @andi_i32(i32 signext %in) signext {
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%tmp38 = and i32 %in, 37
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ret i32 %tmp38
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}
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define i32 @andi_i32_1(i32 %in) {
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%tmp37 = and i32 %in, 37
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ret i32 %tmp37
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}
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; ANDHI instruction generation (i16 data type):
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define <8 x i16> @andhi_v8i16_1(<8 x i16> %in) {
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%tmp2 = and <8 x i16> %in, < i16 511, i16 511, i16 511, i16 511,
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i16 511, i16 511, i16 511, i16 511 >
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ret <8 x i16> %tmp2
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}
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define <8 x i16> @andhi_v8i16_2(<8 x i16> %in) {
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%tmp2 = and <8 x i16> %in, < i16 510, i16 510, i16 510, i16 510,
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i16 510, i16 510, i16 510, i16 510 >
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ret <8 x i16> %tmp2
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}
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define <8 x i16> @andhi_v8i16_3(<8 x i16> %in) {
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%tmp2 = and <8 x i16> %in, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1,
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i16 -1, i16 -1, i16 -1 >
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ret <8 x i16> %tmp2
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}
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define <8 x i16> @andhi_v8i16_4(<8 x i16> %in) {
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%tmp2 = and <8 x i16> %in, < i16 -512, i16 -512, i16 -512, i16 -512,
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i16 -512, i16 -512, i16 -512, i16 -512 >
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ret <8 x i16> %tmp2
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}
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define i16 @andhi_u16(i16 zeroext %in) zeroext {
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%tmp37 = and i16 %in, 37 ; <i16> [#uses=1]
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ret i16 %tmp37
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}
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define i16 @andhi_i16(i16 signext %in) signext {
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%tmp38 = and i16 %in, 37 ; <i16> [#uses=1]
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ret i16 %tmp38
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}
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; i8 data type (s/b ANDBI if 8-bit registers were supported):
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define <16 x i8> @and_v16i8(<16 x i8> %in) {
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; ANDBI generated for vector types
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%tmp2 = and <16 x i8> %in, < i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
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i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
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i8 42, i8 42, i8 42, i8 42 >
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ret <16 x i8> %tmp2
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}
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define i8 @and_u8(i8 zeroext %in) zeroext {
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; ANDBI generated:
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%tmp37 = and i8 %in, 37
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ret i8 %tmp37
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}
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define i8 @and_sext8(i8 signext %in) signext {
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; ANDBI generated
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%tmp38 = and i8 %in, 37
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ret i8 %tmp38
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}
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define i8 @and_i8(i8 %in) {
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; ANDBI generated
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%tmp38 = and i8 %in, 205
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ret i8 %tmp38
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}
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