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llvm-6502/lib/Target/R600
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Tom Stellard 1d8c7eb225 R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205732 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-07 19:45:45 +00:00
..
InstPrinter
Make methods static
2014-03-17 22:23:09 +00:00
MCTargetDesc
Completely rewrite ELFObjectWriter::RecordRelocation.
2014-03-29 06:26:49 +00:00
TargetInfo
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AMDGPU.h
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AMDGPU.td
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AMDGPUAsmPrinter.cpp
R600/SI: Use correct dest register class for V_READFIRSTLANE_B32
2014-03-17 17:03:51 +00:00
AMDGPUAsmPrinter.h
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AMDGPUCallingConv.td
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AMDGPUConvertToISA.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUInstrInfo.cpp
Fix indentation
2014-03-11 00:01:27 +00:00
AMDGPUInstrInfo.h
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AMDGPUInstrInfo.td
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
2014-04-07 19:45:41 +00:00
AMDGPUInstructions.td
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
2014-04-07 19:45:41 +00:00
AMDGPUIntrinsics.td
R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.
2014-03-31 18:21:18 +00:00
AMDGPUISelDAGToDAG.cpp
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
2014-04-07 19:45:41 +00:00
AMDGPUISelLowering.cpp
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
2014-04-07 19:45:41 +00:00
AMDGPUISelLowering.h
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
2014-04-07 19:45:41 +00:00
AMDGPUMachineFunction.cpp
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AMDGPUMachineFunction.h
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AMDGPUMCInstLower.cpp
MachineInstr: introduce explicit_operands and implicit_operands ranges
2014-04-05 22:42:04 +00:00
AMDGPUMCInstLower.h
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AMDGPURegisterInfo.cpp
Make consistent use of MCPhysReg instead of uint16_t throughout the tree.
2014-04-04 05:16:06 +00:00
AMDGPURegisterInfo.h
Make consistent use of MCPhysReg instead of uint16_t throughout the tree.
2014-04-04 05:16:06 +00:00
AMDGPURegisterInfo.td
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AMDGPUSubtarget.cpp
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AMDGPUSubtarget.h
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
2014-04-07 19:45:41 +00:00
AMDGPUTargetMachine.cpp
R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()
2014-03-21 15:51:57 +00:00
AMDGPUTargetMachine.h
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AMDGPUTargetTransformInfo.cpp
Fix tabs
2014-04-04 20:13:08 +00:00
AMDILBase.td
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AMDILCFGStructurizer.cpp
R600: Don't viewCFG() under DEBUG() except on failure.
2014-03-24 20:29:02 +00:00
AMDILInstrInfo.td
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AMDILIntrinsicInfo.cpp
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AMDILIntrinsicInfo.h
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AMDILIntrinsics.td
R600: Match sign_extend_inreg to BFE instructions
2014-03-17 18:58:11 +00:00
AMDILISelLowering.cpp
R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp
2014-03-25 18:18:27 +00:00
AMDILRegisterInfo.td
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CaymanInstructions.td
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
2014-04-07 19:45:41 +00:00
CMakeLists.txt
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EvergreenInstructions.td
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
2014-04-07 19:45:41 +00:00
LLVMBuild.txt
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Makefile
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Processors.td
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R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
[C++11] Replace llvm::next and llvm::prior with std::next and std::prev.
2014-03-02 12:27:27 +00:00
R600InstrFormats.td
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R600InstrInfo.cpp
[C++11] Replace llvm::next and llvm::prior with std::next and std::prev.
2014-03-02 12:27:27 +00:00
R600InstrInfo.h
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R600Instructions.td
R600: Reorganize tablegen instruction definitions
2014-03-24 16:07:25 +00:00
R600Intrinsics.td
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R600ISelLowering.cpp
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
2014-04-07 19:45:41 +00:00
R600ISelLowering.h
R600/SI: Fix unreachable with a sext_in_reg to an illegal type.
2014-03-27 17:23:24 +00:00
R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
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R600MachineScheduler.h
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R600OptimizeVectorRegisters.cpp
Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing
2014-03-13 23:12:04 +00:00
R600Packetizer.cpp
[C++11] Replace llvm::next and llvm::prior with std::next and std::prev.
2014-03-02 12:27:27 +00:00
R600RegisterInfo.cpp
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R600RegisterInfo.h
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R600RegisterInfo.td
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R600Schedule.td
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R600TextureIntrinsicsReplacer.cpp
[Layering] Move InstVisitor.h into the IR library as it is pretty
2014-03-06 03:23:41 +00:00
R700Instructions.td
R600: Reorganize tablegen instruction definitions
2014-03-24 16:07:25 +00:00
SIAnnotateControlFlow.cpp
Add DEBUG_TYPE to SIAnnotateControlFlow
2014-02-03 22:58:05 +00:00
SIDefines.h
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SIFixSGPRCopies.cpp
R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies
2014-04-07 19:45:45 +00:00
SIInsertWaits.cpp
R600/SI: Add intrinsic for S_SENDMSG instruction
2014-01-27 07:20:44 +00:00
SIInstrFormats.td
R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()
2014-03-21 15:51:57 +00:00
SIInstrInfo.cpp
R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies
2014-04-07 19:45:45 +00:00
SIInstrInfo.h
R600/SI: Implement shouldConvertConstantLoadToIntImm
2014-03-31 19:54:27 +00:00
SIInstrInfo.td
R600/SI: Lower 64-bit immediates using REG_SEQUENCE
2014-04-03 20:19:27 +00:00
SIInstructions.td
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
2014-04-07 19:45:41 +00:00
SIIntrinsics.td
R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions
2014-01-27 07:20:51 +00:00
SIISelLowering.cpp
R600: Match 24-bit arithmetic patterns in a Target DAGCombine
2014-04-07 19:45:41 +00:00
SIISelLowering.h
Change shouldSplitVectorElementType to better match the description.
2014-03-31 20:54:58 +00:00
SILowerControlFlow.cpp
R600: avoid calling std::next on an iterator that might be end()
2014-03-28 13:52:56 +00:00
SIMachineFunctionInfo.cpp
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SIMachineFunctionInfo.h
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SIRegisterInfo.cpp
R600/SI: Return the correct index for VGPRs in getHWRegIndex()
2014-03-31 14:01:52 +00:00
SIRegisterInfo.h
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SIRegisterInfo.td
R600/SI: Use correct dest register class for V_READFIRSTLANE_B32
2014-03-17 17:03:51 +00:00
SISchedule.td
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SITypeRewriter.cpp
[Layering] Move InstVisitor.h into the IR library as it is pretty
2014-03-06 03:23:41 +00:00