Chris Lattner 0a9481f44f Enhance ComputeMaskedBits to know that aligned frameindexes ... have their low bits set to zero. This allows us to optimize out explicit stack alignment code like in stack-align.ll:test4 when it is redundant. Doing this causes the code generator to start turning FI+cst into FI|cst all over the place, which is general goodness (that is the canonical form) except that various pieces of the code generator don't handle OR aggressively. Fix this by introducing a new SelectionDAG::isBaseWithConstantOffset predicate, and using it in places that are looking for ADD(X,CST). The ARM backend in particular was missing a lot of addressing mode folding opportunities around OR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125470 91177308-0d34-0410-b5e6-96231b3b80d8		2011-02-13 22:25:43 +00:00
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Alpha
ARM	Implement sdiv & udiv for <4 x i16> and <8 x i8> NEON vector types.	2011-02-11 20:53:29 +00:00
Blackfin
CBackend
CellSPU	fix visitShift to properly zero extend the shift amount if the provided operand	2011-02-13 09:02:52 +00:00
CPP
Generic	A fix for 9165.	2011-02-12 14:40:33 +00:00
MBlaze	fix visitShift to properly zero extend the shift amount if the provided operand	2011-02-13 09:02:52 +00:00
Mips	Disable this test for now...	2011-02-11 02:59:08 +00:00
MSP430	Enhance ComputeMaskedBits to know that aligned frameindexes	2011-02-13 22:25:43 +00:00
PowerPC
PTX	ptx: add passing parameter to kernel functions	2011-02-10 12:01:24 +00:00
SPARC	Prevent IMPLICIT_DEF/KILL to become a delay filler instruction in SPARC backend.	2011-02-12 19:02:33 +00:00
SystemZ
Thumb	Sorry, several patches in one.	2011-01-20 08:34:58 +00:00
Thumb2	Move a test that ended up in the wrong place.	2011-02-05 04:15:50 +00:00
X86	Enhance ComputeMaskedBits to know that aligned frameindexes	2011-02-13 22:25:43 +00:00
XCore	Add intrinsic for setc instruction on the XCore.	2011-02-09 13:22:12 +00:00