Ulrich Weigand 0b8594268f [PowerPC] Support symbolic u16imm operands ... Currently, all instructions taking s16imm operands support symbolic operands. However, for u16imm operands, we only support actual immediate integers. This causes the assembler to reject code like ori %r5, %r5, symbol@l This patch changes the u16imm operand definition to likewise accept symbolic operands. In fact, s16imm and u16imm can share the same encoding routine, now renamed to getImm16Encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184944 91177308-0d34-0410-b5e6-96231b3b80d8		2013-06-26 13:49:15 +00:00
..
AArch64	AArch64: fix overzealous NEXTing for Windows testing.	2013-06-23 15:32:01 +00:00
ARM	ARM: fix thumb1 nop decoding	2013-06-24 09:11:53 +00:00
AsmParser
COFF
Disassembler	ARM: operands should be explicit when disassembled	2013-06-26 13:39:07 +00:00
ELF	[MC/DWARF] Generate multiple .debug_line entries for adjacent .loc directives	2013-06-19 21:27:27 +00:00
MachO
Markup
MBlaze
Mips	Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU registers.	2013-06-20 11:21:49 +00:00
PowerPC	[PowerPC] Support symbolic u16imm operands	2013-06-26 13:49:15 +00:00
SystemZ	[SystemZ] Immediate compare-and-branch support	2013-05-29 11:58:52 +00:00
X86	Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.	2013-06-18 17:08:10 +00:00