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42f562a169
This option is used when the user wants to avoid emitting double precision FP loads and stores. Double precision FP loads and stores are expanded to single precision instructions after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8
536 lines
23 KiB
TableGen
536 lines
23 KiB
TableGen
//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Mips FPU instruction set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Floating Point Instructions
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// ------------------------
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// * 64bit fp:
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// - 32 64-bit registers (default mode)
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// - 16 even 32-bit registers (32-bit compatible mode) for
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// single and double access.
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// * 32bit fp:
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// - 16 even 32-bit registers - single and double (aliased)
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// - 32 32-bit registers (within single-only mode)
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//===----------------------------------------------------------------------===//
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// Floating Point Compare and Branch
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def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
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SDTCisVT<1, OtherVT>]>;
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def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
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SDTCisVT<2, i32>]>;
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def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
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SDTCisSameAs<1, 2>]>;
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def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
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SDTCisVT<1, i32>,
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SDTCisSameAs<1, 2>]>;
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def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
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SDTCisVT<1, f64>,
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SDTCisVT<2, i32>]>;
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def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
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def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
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def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
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def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
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[SDNPHasChain, SDNPOptInGlue]>;
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def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
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def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
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SDT_MipsExtractElementF64>;
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// Operand for printing out a condition code.
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let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
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def condcode : Operand<i32>;
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//===----------------------------------------------------------------------===//
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// Feature predicates.
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//===----------------------------------------------------------------------===//
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def IsFP64bit : Predicate<"Subtarget.isFP64bit()">,
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AssemblerPredicate<"FeatureFP64Bit">;
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def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">,
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AssemblerPredicate<"!FeatureFP64Bit">;
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def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">,
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AssemblerPredicate<"FeatureSingleFloat">;
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def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
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AssemblerPredicate<"!FeatureSingleFloat">;
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// FP immediate patterns.
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def fpimm0 : PatLeaf<(fpimm), [{
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return N->isExactlyValue(+0.0);
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}]>;
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def fpimm0neg : PatLeaf<(fpimm), [{
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return N->isExactlyValue(-0.0);
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}]>;
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//
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// A set of multiclasses is used to address the register usage.
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//
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// S32 - single precision in 16 32bit even fp registers
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// single precision in 32 32bit fp registers in SingleOnly mode
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// S64 - single precision in 32 64bit fp registers (In64BitMode)
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// D32 - double precision in 16 32bit even fp registers
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// D64 - double precision in 32 64bit fp registers (In64BitMode)
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//
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// Only S32 and D32 are supported right now.
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//===----------------------------------------------------------------------===//
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class ADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin, bit IsComm,
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SDPatternOperator OpNode= null_frag> :
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InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
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!strconcat(opstr, "\t$fd, $fs, $ft"),
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[(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR> {
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let isCommutable = IsComm;
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}
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multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
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SDPatternOperator OpNode = null_frag> {
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def _D32 : ADDS_FT<opstr, AFGR64, Itin, IsComm, OpNode>,
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Requires<[NotFP64bit, HasStdEnc]>;
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def _D64 : ADDS_FT<opstr, FGR64, Itin, IsComm, OpNode>,
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Requires<[IsFP64bit, HasStdEnc]> {
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string DecoderNamespace = "Mips64";
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}
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}
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class ABSS_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
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InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
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InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
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[(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>,
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NeverHasSideEffects;
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multiclass ABSS_M<string opstr, InstrItinClass Itin,
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SDPatternOperator OpNode= null_frag> {
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def _D32 : ABSS_FT<opstr, AFGR64, AFGR64, Itin, OpNode>,
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Requires<[NotFP64bit, HasStdEnc]>;
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def _D64 : ABSS_FT<opstr, FGR64, FGR64, Itin, OpNode>,
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Requires<[IsFP64bit, HasStdEnc]> {
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string DecoderNamespace = "Mips64";
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}
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}
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multiclass ROUND_M<string opstr, InstrItinClass Itin> {
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def _D32 : ABSS_FT<opstr, FGR32, AFGR64, Itin>,
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Requires<[NotFP64bit, HasStdEnc]>;
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def _D64 : ABSS_FT<opstr, FGR32, FGR64, Itin>,
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Requires<[IsFP64bit, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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}
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}
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class MFC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
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InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
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InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
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[(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
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class MTC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
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InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
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InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
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[(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
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class MFC1_FT_CCR<string opstr, RegisterClass DstRC, RegisterOperand SrcRC,
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InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
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InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
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[(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
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class MTC1_FT_CCR<string opstr, RegisterOperand DstRC, RegisterClass SrcRC,
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InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
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InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
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[(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
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class LW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
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Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
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InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI> {
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let DecoderMethod = "DecodeFMem";
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let mayLoad = 1;
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}
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class SW_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
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Operand MemOpnd, SDPatternOperator OpNode= null_frag> :
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InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
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[(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI> {
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let DecoderMethod = "DecodeFMem";
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let mayStore = 1;
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}
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class MADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
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SDPatternOperator OpNode = null_frag> :
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InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
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!strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
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[(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>;
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class NMADDS_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
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SDPatternOperator OpNode = null_frag> :
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InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
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!strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
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[(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
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Itin, FrmFR>;
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class LWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
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InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
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InstSE<(outs DRC:$fd), (ins PRC:$base, PRC:$index),
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!strconcat(opstr, "\t$fd, ${index}(${base})"),
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[(set DRC:$fd, (OpNode (add PRC:$base, PRC:$index)))], Itin, FrmFI> {
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let AddedComplexity = 20;
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}
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class SWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC,
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InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
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InstSE<(outs), (ins DRC:$fs, PRC:$base, PRC:$index),
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!strconcat(opstr, "\t$fs, ${index}(${base})"),
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[(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI> {
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let AddedComplexity = 20;
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}
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class BC1F_FT<string opstr, InstrItinClass Itin,
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SDPatternOperator Op = null_frag> :
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InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
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[(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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let Defs = [AT];
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let Uses = [FCR31];
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}
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class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
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SDPatternOperator OpNode = null_frag> :
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InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
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!strconcat("c.$cond.", typestr, "\t$fs, $ft"),
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[(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR> {
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let Defs = [FCR31];
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}
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//===----------------------------------------------------------------------===//
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// Floating Point Instructions
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//===----------------------------------------------------------------------===//
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def ROUND_W_S : ABSS_FT<"round.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xc, 16>;
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def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xd, 16>;
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def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xe, 16>;
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def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xf, 16>;
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def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0x24, 16>;
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defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
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defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>;
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defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>;
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defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
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defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>;
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let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
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def ROUND_L_S : ABSS_FT<"round.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x8, 16>;
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def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64, FGR64, IIFcvt>,
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ABSS_FM<0x8, 17>;
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def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x9, 16>;
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def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64, FGR64, IIFcvt>,
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ABSS_FM<0x9, 17>;
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def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xa, 16>;
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def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0xa, 17>;
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def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xb, 16>;
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def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64, FGR64, IIFcvt>,
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ABSS_FM<0xb, 17>;
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}
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def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32, FGR32, IIFcvt>, ABSS_FM<0x20, 20>;
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def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x25, 16>;
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def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0x25, 17>;
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let Predicates = [NotFP64bit, HasStdEnc] in {
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def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32, AFGR64, IIFcvt>, ABSS_FM<0x20, 17>;
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def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
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def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
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}
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let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
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def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 17>;
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def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 21>;
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def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
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def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
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def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64, FGR64, IIFcvt>, ABSS_FM<0x21, 21>;
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}
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let Predicates = [NoNaNsFPMath, HasStdEnc] in {
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def FABS_S : ABSS_FT<"abs.s", FGR32, FGR32, IIFcvt, fabs>, ABSS_FM<0x5, 16>;
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def FNEG_S : ABSS_FT<"neg.s", FGR32, FGR32, IIFcvt, fneg>, ABSS_FM<0x7, 16>;
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defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
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defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
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}
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def FSQRT_S : ABSS_FT<"sqrt.s", FGR32, FGR32, IIFsqrtSingle, fsqrt>,
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ABSS_FM<0x4, 16>;
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defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
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// The odd-numbered registers are only referenced when doing loads,
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// stores, and moves between floating-point and integer registers.
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// When defining instructions, we reference all 32-bit registers,
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// regardless of register aliasing.
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/// Move Control Registers From/To CPU Registers
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def CFC1 : MFC1_FT_CCR<"cfc1", CPURegs, CCROpnd, IIFmove>, MFC1_FM<2>;
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def CTC1 : MTC1_FT_CCR<"ctc1", CCROpnd, CPURegs, IIFmove>, MFC1_FM<6>;
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def MFC1 : MFC1_FT<"mfc1", CPURegs, FGR32, IIFmove, bitconvert>, MFC1_FM<0>;
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def MTC1 : MTC1_FT<"mtc1", FGR32, CPURegs, IIFmove, bitconvert>, MFC1_FM<4>;
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def DMFC1 : MFC1_FT<"dmfc1", CPU64Regs, FGR64, IIFmove, bitconvert>, MFC1_FM<1>;
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def DMTC1 : MTC1_FT<"dmtc1", FGR64, CPU64Regs, IIFmove, bitconvert>, MFC1_FM<5>;
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def FMOV_S : ABSS_FT<"mov.s", FGR32, FGR32, IIFmove>, ABSS_FM<0x6, 16>;
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def FMOV_D32 : ABSS_FT<"mov.d", AFGR64, AFGR64, IIFmove>, ABSS_FM<0x6, 17>,
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Requires<[NotFP64bit, HasStdEnc]>;
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def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>,
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Requires<[IsFP64bit, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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}
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/// Floating Point Memory Instructions
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let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
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def LWC1_P8 : LW_FT<"lwc1", FGR32, IILoad, mem64, load>, LW_FM<0x31>;
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def SWC1_P8 : SW_FT<"swc1", FGR32, IIStore, mem64, store>, LW_FM<0x39>;
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def LDC164_P8 : LW_FT<"ldc1", FGR64, IILoad, mem64, load>, LW_FM<0x35> {
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let isCodeGenOnly =1;
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}
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def SDC164_P8 : SW_FT<"sdc1", FGR64, IIStore, mem64, store>, LW_FM<0x3d> {
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let isCodeGenOnly =1;
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}
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}
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let Predicates = [NotN64, HasStdEnc] in {
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def LWC1 : LW_FT<"lwc1", FGR32, IILoad, mem, load>, LW_FM<0x31>;
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def SWC1 : SW_FT<"swc1", FGR32, IIStore, mem, store>, LW_FM<0x39>;
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}
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let Predicates = [NotN64, HasMips64, HasStdEnc],
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DecoderNamespace = "Mips64" in {
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def LDC164 : LW_FT<"ldc1", FGR64, IILoad, mem, load>, LW_FM<0x35>;
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def SDC164 : SW_FT<"sdc1", FGR64, IIStore, mem, store>, LW_FM<0x3d>;
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}
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let Predicates = [NotN64, NotMips64, HasStdEnc] in {
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let isPseudo = 1, isCodeGenOnly = 1 in {
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def PseudoLDC1 : LW_FT<"", AFGR64, IILoad, mem, load>;
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def PseudoSDC1 : SW_FT<"", AFGR64, IIStore, mem, store>;
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}
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def LDC1 : LW_FT<"ldc1", AFGR64, IILoad, mem>, LW_FM<0x35>;
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def SDC1 : SW_FT<"sdc1", AFGR64, IIStore, mem>, LW_FM<0x3d>;
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}
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// Indexed loads and stores.
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let Predicates = [HasFPIdx, HasStdEnc] in {
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def LWXC1 : LWXC1_FT<"lwxc1", FGR32, CPURegs, IILoad, load>, LWXC1_FM<0>;
|
|
def SWXC1 : SWXC1_FT<"swxc1", FGR32, CPURegs, IIStore, store>, SWXC1_FM<8>;
|
|
}
|
|
|
|
let Predicates = [HasMips32r2, NotMips64, HasStdEnc] in {
|
|
def LDXC1 : LWXC1_FT<"ldxc1", AFGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
|
|
def SDXC1 : SWXC1_FT<"sdxc1", AFGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
|
|
}
|
|
|
|
let Predicates = [HasMips64, NotN64, HasStdEnc], DecoderNamespace="Mips64" in {
|
|
def LDXC164 : LWXC1_FT<"ldxc1", FGR64, CPURegs, IILoad, load>, LWXC1_FM<1>;
|
|
def SDXC164 : SWXC1_FT<"sdxc1", FGR64, CPURegs, IIStore, store>, SWXC1_FM<9>;
|
|
}
|
|
|
|
// n64
|
|
let Predicates = [IsN64, HasStdEnc], isCodeGenOnly=1 in {
|
|
def LWXC1_P8 : LWXC1_FT<"lwxc1", FGR32, CPU64Regs, IILoad, load>, LWXC1_FM<0>;
|
|
def LDXC164_P8 : LWXC1_FT<"ldxc1", FGR64, CPU64Regs, IILoad, load>,
|
|
LWXC1_FM<1>;
|
|
def SWXC1_P8 : SWXC1_FT<"swxc1", FGR32, CPU64Regs, IIStore, store>,
|
|
SWXC1_FM<8>;
|
|
def SDXC164_P8 : SWXC1_FT<"sdxc1", FGR64, CPU64Regs, IIStore, store>,
|
|
SWXC1_FM<9>;
|
|
}
|
|
|
|
// Load/store doubleword indexed unaligned.
|
|
let Predicates = [NotMips64, HasStdEnc] in {
|
|
def LUXC1 : LWXC1_FT<"luxc1", AFGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
|
|
def SUXC1 : SWXC1_FT<"suxc1", AFGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
|
|
}
|
|
|
|
let Predicates = [HasMips64, HasStdEnc],
|
|
DecoderNamespace="Mips64" in {
|
|
def LUXC164 : LWXC1_FT<"luxc1", FGR64, CPURegs, IILoad>, LWXC1_FM<0x5>;
|
|
def SUXC164 : SWXC1_FT<"suxc1", FGR64, CPURegs, IIStore>, SWXC1_FM<0xd>;
|
|
}
|
|
|
|
/// Floating-point Aritmetic
|
|
def FADD_S : ADDS_FT<"add.s", FGR32, IIFadd, 1, fadd>, ADDS_FM<0x00, 16>;
|
|
defm FADD : ADDS_M<"add.d", IIFadd, 1, fadd>, ADDS_FM<0x00, 17>;
|
|
def FDIV_S : ADDS_FT<"div.s", FGR32, IIFdivSingle, 0, fdiv>, ADDS_FM<0x03, 16>;
|
|
defm FDIV : ADDS_M<"div.d", IIFdivDouble, 0, fdiv>, ADDS_FM<0x03, 17>;
|
|
def FMUL_S : ADDS_FT<"mul.s", FGR32, IIFmulSingle, 1, fmul>, ADDS_FM<0x02, 16>;
|
|
defm FMUL : ADDS_M<"mul.d", IIFmulDouble, 1, fmul>, ADDS_FM<0x02, 17>;
|
|
def FSUB_S : ADDS_FT<"sub.s", FGR32, IIFadd, 0, fsub>, ADDS_FM<0x01, 16>;
|
|
defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
|
|
|
|
let Predicates = [HasMips32r2, HasStdEnc] in {
|
|
def MADD_S : MADDS_FT<"madd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<4, 0>;
|
|
def MSUB_S : MADDS_FT<"msub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<5, 0>;
|
|
}
|
|
|
|
let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
|
|
def NMADD_S : NMADDS_FT<"nmadd.s", FGR32, IIFmulSingle, fadd>, MADDS_FM<6, 0>;
|
|
def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<7, 0>;
|
|
}
|
|
|
|
let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
|
|
def MADD_D32 : MADDS_FT<"madd.d", AFGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
|
|
def MSUB_D32 : MADDS_FT<"msub.d", AFGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
|
|
}
|
|
|
|
let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
|
|
def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64, IIFmulDouble, fadd>,
|
|
MADDS_FM<6, 1>;
|
|
def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64, IIFmulDouble, fsub>,
|
|
MADDS_FM<7, 1>;
|
|
}
|
|
|
|
let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
|
|
def MADD_D64 : MADDS_FT<"madd.d", FGR64, IIFmulDouble, fadd>, MADDS_FM<4, 1>;
|
|
def MSUB_D64 : MADDS_FT<"msub.d", FGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
|
|
}
|
|
|
|
let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
|
|
isCodeGenOnly=1 in {
|
|
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64, IIFmulDouble, fadd>,
|
|
MADDS_FM<6, 1>;
|
|
def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64, IIFmulDouble, fsub>,
|
|
MADDS_FM<7, 1>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Floating Point Branch Codes
|
|
//===----------------------------------------------------------------------===//
|
|
// Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
|
|
// They must be kept in synch.
|
|
def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
|
|
def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
|
|
|
|
let DecoderMethod = "DecodeBC1" in {
|
|
def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>;
|
|
def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>;
|
|
}
|
|
//===----------------------------------------------------------------------===//
|
|
// Floating Point Flag Conditions
|
|
//===----------------------------------------------------------------------===//
|
|
// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
|
|
// They must be kept in synch.
|
|
def MIPS_FCOND_F : PatLeaf<(i32 0)>;
|
|
def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
|
|
def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
|
|
def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
|
|
def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
|
|
def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
|
|
def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
|
|
def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
|
|
def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
|
|
def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
|
|
def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
|
|
def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
|
|
def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
|
|
def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
|
|
def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
|
|
def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
|
|
|
|
/// Floating Point Compare
|
|
def FCMP_S32 : CEQS_FT<"s", FGR32, IIFcmp, MipsFPCmp>, CEQS_FM<16>;
|
|
def FCMP_D32 : CEQS_FT<"d", AFGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
|
|
Requires<[NotFP64bit, HasStdEnc]>;
|
|
let DecoderNamespace = "Mips64" in
|
|
def FCMP_D64 : CEQS_FT<"d", FGR64, IIFcmp, MipsFPCmp>, CEQS_FM<17>,
|
|
Requires<[IsFP64bit, HasStdEnc]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Floating Point Pseudo-Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
def MOVCCRToCCR : PseudoSE<(outs CCR:$dst), (ins CCROpnd:$src), []>;
|
|
|
|
// This pseudo instr gets expanded into 2 mtc1 instrs after register
|
|
// allocation.
|
|
def BuildPairF64 :
|
|
PseudoSE<(outs AFGR64:$dst),
|
|
(ins CPURegs:$lo, CPURegs:$hi),
|
|
[(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
|
|
|
|
// This pseudo instr gets expanded into 2 mfc1 instrs after register
|
|
// allocation.
|
|
// if n is 0, lower part of src is extracted.
|
|
// if n is 1, higher part of src is extracted.
|
|
def ExtractElementF64 :
|
|
PseudoSE<(outs CPURegs:$dst), (ins AFGR64:$src, i32imm:$n),
|
|
[(set CPURegs:$dst, (MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Floating Point Patterns
|
|
//===----------------------------------------------------------------------===//
|
|
def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
|
|
def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
|
|
|
|
def : MipsPat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
|
|
def : MipsPat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
|
|
|
|
let Predicates = [NotFP64bit, HasStdEnc] in {
|
|
def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
|
|
(CVT_D32_W (MTC1 CPURegs:$src))>;
|
|
def : MipsPat<(i32 (fp_to_sint AFGR64:$src)),
|
|
(MFC1 (TRUNC_W_D32 AFGR64:$src))>;
|
|
def : MipsPat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
|
|
def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
|
|
}
|
|
|
|
let Predicates = [IsFP64bit, HasStdEnc] in {
|
|
def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
|
|
def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
|
|
|
|
def : MipsPat<(f64 (sint_to_fp CPURegs:$src)),
|
|
(CVT_D64_W (MTC1 CPURegs:$src))>;
|
|
def : MipsPat<(f32 (sint_to_fp CPU64Regs:$src)),
|
|
(CVT_S_L (DMTC1 CPU64Regs:$src))>;
|
|
def : MipsPat<(f64 (sint_to_fp CPU64Regs:$src)),
|
|
(CVT_D64_L (DMTC1 CPU64Regs:$src))>;
|
|
|
|
def : MipsPat<(i32 (fp_to_sint FGR64:$src)),
|
|
(MFC1 (TRUNC_W_D64 FGR64:$src))>;
|
|
def : MipsPat<(i64 (fp_to_sint FGR32:$src)), (DMFC1 (TRUNC_L_S FGR32:$src))>;
|
|
def : MipsPat<(i64 (fp_to_sint FGR64:$src)),
|
|
(DMFC1 (TRUNC_L_D64 FGR64:$src))>;
|
|
|
|
def : MipsPat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
|
|
def : MipsPat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
|
|
}
|
|
|
|
// Patterns for loads/stores with a reg+imm operand.
|
|
let AddedComplexity = 40 in {
|
|
let Predicates = [IsN64, HasStdEnc] in {
|
|
def : LoadRegImmPat<LWC1_P8, f32, load>;
|
|
def : StoreRegImmPat<SWC1_P8, f32>;
|
|
def : LoadRegImmPat<LDC164_P8, f64, load>;
|
|
def : StoreRegImmPat<SDC164_P8, f64>;
|
|
}
|
|
|
|
let Predicates = [NotN64, HasStdEnc] in {
|
|
def : LoadRegImmPat<LWC1, f32, load>;
|
|
def : StoreRegImmPat<SWC1, f32>;
|
|
}
|
|
|
|
let Predicates = [NotN64, HasMips64, HasStdEnc] in {
|
|
def : LoadRegImmPat<LDC164, f64, load>;
|
|
def : StoreRegImmPat<SDC164, f64>;
|
|
}
|
|
|
|
let Predicates = [NotN64, NotMips64, HasStdEnc] in {
|
|
def : LoadRegImmPat<PseudoLDC1, f64, load>;
|
|
def : StoreRegImmPat<PseudoSDC1, f64>;
|
|
}
|
|
}
|