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0bbfc9313c
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182286 91177308-0d34-0410-b5e6-96231b3b80d8
40 lines
1.1 KiB
LLVM
40 lines
1.1 KiB
LLVM
; RUN: llc < %s -debug-only=isel -march=r600 -mcpu=redwood -o - 2>&1 | FileCheck --check-prefix=R600-CHECK %s
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; RUN: llc < %s -debug-only=isel -march=r600 -mcpu=SI -o - 2>&1 | FileCheck --check-prefix=SI-CHECK %s
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; R600-CHECK: rotr
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; R600-CHECK: @rotr
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; R600-CHECK: BIT_ALIGN_INT
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; SI-CHECK: rotr
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; SI-CHECK: @rotr
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; SI-CHECK: V_ALIGNBIT_B32
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define void @rotr(i32 addrspace(1)* %in, i32 %x, i32 %y) {
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entry:
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%0 = sub i32 32, %y
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%1 = shl i32 %x, %0
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%2 = lshr i32 %x, %y
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%3 = or i32 %1, %2
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store i32 %3, i32 addrspace(1)* %in
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ret void
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}
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; R600-CHECK: rotr
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; R600-CHECK: @rotl
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; R600-CHECK: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x
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; R600-CHECK-NEXT: 32
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; R600-CHECK: BIT_ALIGN_INT {{\** T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PV.[xyzw]}}
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; SI-CHECK: rotr
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; SI-CHECK: @rotl
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; SI-CHECK: V_SUB_I32_e32 [[DST:VGPR[0-9]+]], 32, {{VGPR[0-9]+}}
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; SI-CHECK: V_ALIGNBIT_B32 {{VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}, [[DST]]
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define void @rotl(i32 addrspace(1)* %in, i32 %x, i32 %y) {
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entry:
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%0 = shl i32 %x, %y
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%1 = sub i32 32, %y
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%2 = lshr i32 %x, %1
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%3 = or i32 %0, %2
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store i32 %3, i32 addrspace(1)* %in
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ret void
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}
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