Jim Grosbach 0c2ff8cbfd ARM: Thumb2 LDR(literal) can target SP. ... Fix a slightly overzealous destination register restriction for the 'without .w' alias. Add some explicit testcases. rdar://16033140 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201173 91177308-0d34-0410-b5e6-96231b3b80d8		2014-02-11 20:48:39 +00:00
..
AArch64	[AArch64] Handle aliases of conditional branches without b.pred form.	2014-02-10 15:43:11 +00:00
ARM	ARM: Thumb2 LDR(literal) can target SP.	2014-02-11 20:48:39 +00:00
AsmParser	AsmParser: Parse (and ignore) nested .macro definitions.	2014-02-09 16:22:00 +00:00
COFF	Fix PR18381 - print a minimal diagnostic rather than assert on unresolved .secidx target	2014-01-30 21:13:05 +00:00
Disassembler	[Sparc] Correct quad register list in the asm parser.	2014-01-24 05:24:01 +00:00
ELF	MC: Add support for .cfi_startproc simple	2014-01-27 17:20:25 +00:00
MachO	Fix known typos	2014-01-24 17:20:08 +00:00
Markup
Mips	[mips][msa] Add DLSA instruction.	2014-02-10 12:05:17 +00:00
PowerPC	Convert another llc -filetype=obj test.	2013-10-28 22:17:19 +00:00
Sparc	[Sparc] Add support for parsing synthetic instruction 'mov'.	2014-02-07 09:06:52 +00:00
SystemZ	[SystemZ] Add MC support for interlocked-access 1 instructions	2013-12-24 15:14:05 +00:00
X86	AVX-512: Optimized BUILD_VECTOR pattern;	2014-02-11 07:25:59 +00:00