Matt Arsenault 0c6d96cf16 R600: Implement isZExtFree. ...

This allows 64-bit operations that are truncated to be reduced
to 32-bit ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204946 91177308-0d34-0410-b5e6-96231b3b80d8

2014-03-27 17:23:31 +00:00

..

AArch64

[AArch64] Lower SHL_PARTS, SRA_PARTS and SRL_PARTS

2014-03-27 16:28:09 +00:00

ARM

ARM: add intrinsics for the v8 ldaex/stlex

2014-03-26 14:39:31 +00:00

CPP

Begin adding docs and IR-level support for the inalloca attribute

2013-12-19 02:14:12 +00:00

Generic

CommandLine: Exit successfully for -version and -help

2014-02-28 19:08:01 +00:00

Hexagon

Fix broken CHECK lines

2014-02-16 07:31:05 +00:00

Inputs

…

Mips

Add @llvm.clear_cache builtin

2014-03-26 12:52:28 +00:00

MSP430

Fix known typos

2014-01-24 17:20:08 +00:00

NVPTX

Add test to test/CodeGen/NVPTX for "alloca buffer" arguments.

2014-03-24 16:52:30 +00:00

PowerPC

[PowerPC] Generate VSX permutations for v2[fi]64 vectors

2014-03-26 22:58:37 +00:00

R600

R600: Implement isZExtFree.

2014-03-27 17:23:31 +00:00

SPARC

Remove the linker_private and linker_private_weak linkages.

2014-03-13 23:18:37 +00:00

SystemZ

[SystemZ] Add support for z196 float<->unsigned conversions

2014-03-21 10:56:30 +00:00

Thumb

Add triples to try to fix the windows bots.

2014-02-13 16:49:47 +00:00

Thumb2

ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block

2014-02-26 11:27:28 +00:00

X86

Prevent alias from pointing to weak aliases.

2014-03-27 15:26:56 +00:00

XCore

[XCore] Add support for the "m" inline asm constraint.

2014-03-06 16:37:48 +00:00