Bradley Smith 0ce7616654 [ARM64] Correct more bounds checks/diagnostics for arithmetic shift operands ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208528 91177308-0d34-0410-b5e6-96231b3b80d8

2014-05-12 09:41:43 +00:00

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adr.s

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advsimd.s

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aliases.s

AArch64/ARM64: print BFM instructions as BFI or BFXIL

2014-05-01 12:29:38 +00:00

arithmetic-encoding.s

[ARM64] Correct more bounds checks/diagnostics for arithmetic shift operands

2014-05-12 09:41:43 +00:00

arm64-fixup.s

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basic-a64-instructions.s

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be-datalayout.s

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bitfield-encoding.s

AArch64/ARM64: print BFM instructions as BFI or BFXIL

2014-05-01 12:29:38 +00:00

branch-encoding.s

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condbr-without-dots.s

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crypto.s

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diagno-predicate.s

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diags.s

[ARM64] Correct more bounds checks/diagnostics for arithmetic shift operands

2014-05-12 09:41:43 +00:00

directive_loh.s

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elf-reloc-condbr.s

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elf-relocs.s

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fp-encoding.s

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large-relocs.s

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leaf-compact-unwind.s

Move test to the ARM64 directory.

2014-05-05 16:14:37 +00:00

lit.local.cfg

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logical-encoding.s

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mapping-across-sections.s

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mapping-within-section.s

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memory.s

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nv-cond.s

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optional-hash.s

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separator.s

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simd-ldst.s

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small-data-fixups.s

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spsel-sysreg.s

AArch64/ARM64: produce more informative diagnostic assembling some immediates

2014-05-06 11:18:53 +00:00

system-encoding.s

[ARM64] Conditionalize CPU specific system registers on subtarget features

2014-05-01 10:25:36 +00:00

target-specific-sysreg.s

[ARM64] Conditionalize CPU specific system registers on subtarget features

2014-05-01 10:25:36 +00:00

tls-modifiers-darwin.s

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tls-relocs.s

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v128_lo-diagnostics.s

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variable-exprs.s

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vector-lists.s

AArch64/ARM64: make NEON vector list parsing a bit more robust

2014-05-06 12:50:51 +00:00

verbose-vector-case.s

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