mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-14 16:33:28 +00:00
a6ace00520
Patchpoints already did this. Doing it for stackmaps is a convenience for the runtime in the event that it needs to scratch register to patch or perform a runtime call thunk. Unlike patchpoints, we just assume the AnyRegCC calling convention. This is the only language and target independent calling convention specific to stackmaps so makes sense. Although the calling convention is not currently used to select the scratch registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202943 91177308-0d34-0410-b5e6-96231b3b80d8
462 lines
14 KiB
LLVM
462 lines
14 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -disable-fp-elim | FileCheck %s
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;
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; Note: Print verbose stackmaps using -debug-only=stackmaps.
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; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
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; CHECK-NEXT: __LLVM_StackMaps:
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; CHECK-NEXT: .long 0
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; Num Functions
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; CHECK-NEXT: .long 15
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; CHECK-NEXT: .long _constantargs
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; CHECK-NEXT: .long 8
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; CHECK-NEXT: .long _osrinline
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; CHECK-NEXT: .long 24
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; CHECK-NEXT: .long _osrcold
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; CHECK-NEXT: .long 8
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; CHECK-NEXT: .long _propertyRead
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; CHECK-NEXT: .long 8
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; CHECK-NEXT: .long _propertyWrite
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; CHECK-NEXT: .long 8
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; CHECK-NEXT: .long _jsVoidCall
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; CHECK-NEXT: .long 8
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; CHECK-NEXT: .long _jsIntCall
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; CHECK-NEXT: .long 8
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; CHECK-NEXT: .long _spilledValue
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; CHECK-NEXT: .long 56
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; CHECK-NEXT: .long _spilledStackMapValue
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; CHECK-NEXT: .long 56
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; CHECK-NEXT: .long _spillSubReg
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; CHECK-NEXT: .long 56
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; CHECK-NEXT: .long _subRegOffset
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; CHECK-NEXT: .long 56
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; CHECK-NEXT: .long _liveConstant
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; CHECK-NEXT: .long 8
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; CHECK-NEXT: .long _directFrameIdx
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; CHECK-NEXT: .long 56
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; CHECK-NEXT: .long _longid
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; CHECK-NEXT: .long 8
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; CHECK-NEXT: .long _clobberScratch
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; CHECK-NEXT: .long 56
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; Num LargeConstants
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; CHECK-NEXT: .long 3
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; CHECK-NEXT: .quad 2147483648
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; CHECK-NEXT: .quad 4294967295
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; CHECK-NEXT: .quad 4294967296
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; Num Callsites
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; CHECK-NEXT: .long 19
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; Constant arguments
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;
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .long L{{.*}}-_constantargs
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 12
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; SmallConstant
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long -1
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; SmallConstant
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long -1
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; SmallConstant
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 65536
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; SmallConstant
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 2000000000
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; SmallConstant
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 2147483647
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; SmallConstant
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long -1
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; SmallConstant
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long -1
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; SmallConstant
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; LargeConstant at index 0
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; CHECK-NEXT: .byte 5
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; LargeConstant at index 1
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; CHECK-NEXT: .byte 5
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 1
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; LargeConstant at index 2
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; CHECK-NEXT: .byte 5
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 2
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; SmallConstant
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long -1
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define void @constantargs() {
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entry:
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%0 = inttoptr i64 12345 to i8*
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tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 1, i32 15, i8* %0, i32 0, i16 65535, i16 -1, i32 65536, i32 2000000000, i32 2147483647, i32 -1, i32 4294967295, i32 4294967296, i64 2147483648, i64 4294967295, i64 4294967296, i64 -1)
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ret void
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}
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; Inline OSR Exit
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;
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; CHECK-LABEL: .long L{{.*}}-_osrinline
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 2
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define void @osrinline(i64 %a, i64 %b) {
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entry:
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; Runtime void->void call.
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call void inttoptr (i64 -559038737 to void ()*)()
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; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
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call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
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ret void
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}
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; Cold OSR Exit
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;
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; 2 live variables in register.
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;
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; CHECK-LABEL: .long L{{.*}}-_osrcold
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 2
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define void @osrcold(i64 %a, i64 %b) {
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entry:
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%test = icmp slt i64 %a, %b
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br i1 %test, label %ret, label %cold
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cold:
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; OSR patchpoint with 12-byte nop-slide and 2 live vars.
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%thunk = inttoptr i64 -559038737 to i8*
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call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 4, i32 15, i8* %thunk, i32 0, i64 %a, i64 %b)
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unreachable
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ret:
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ret void
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}
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; Property Read
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; CHECK-LABEL: .long L{{.*}}-_propertyRead
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 2
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define i64 @propertyRead(i64* %obj) {
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entry:
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%resolveRead = inttoptr i64 -559038737 to i8*
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%result = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %resolveRead, i32 1, i64* %obj)
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%add = add i64 %result, 3
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ret i64 %add
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}
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; Property Write
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; CHECK-LABEL: .long L{{.*}}-_propertyWrite
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 2
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
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entry:
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%resolveWrite = inttoptr i64 -559038737 to i8*
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call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 6, i32 15, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
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ret void
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}
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; Void JS Call
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;
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; 2 live variables in registers.
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;
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; CHECK-LABEL: .long L{{.*}}-_jsVoidCall
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 2
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
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entry:
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%resolveCall = inttoptr i64 -559038737 to i8*
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call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 7, i32 15, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
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ret void
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}
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; i64 JS Call
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;
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; 2 live variables in registers.
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;
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; CHECK-LABEL: .long L{{.*}}-_jsIntCall
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 2
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .long 0
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define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
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entry:
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%resolveCall = inttoptr i64 -559038737 to i8*
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%result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 8, i32 15, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
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%add = add i64 %result, 3
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ret i64 %add
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}
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; Spilled stack map values.
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;
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; Verify 17 stack map entries.
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;
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; CHECK-LABEL: .long L{{.*}}-_spilledValue
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 17
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;
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; Check that at least one is a spilled entry from RBP.
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; Location: Indirect RBP + ...
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; CHECK: .byte 3
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 6
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define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) {
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entry:
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call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 11, i32 15, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
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ret void
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}
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; Spilled stack map values.
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;
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; Verify 17 stack map entries.
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;
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; CHECK-LABEL: .long L{{.*}}-_spilledStackMapValue
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 17
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;
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; Check that at least one is a spilled entry from RBP.
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; Location: Indirect RBP + ...
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; CHECK: .byte 3
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 6
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define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) {
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entry:
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call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 12, i32 15, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
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ret void
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}
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; Spill a subregister stackmap operand.
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;
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; CHECK-LABEL: .long L{{.*}}-_spillSubReg
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; CHECK-NEXT: .short 0
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; 4 locations
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; CHECK-NEXT: .short 1
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;
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; Check that the subregister operand is a 4-byte spill.
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; Location: Indirect, 4-byte, RBP + ...
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; CHECK: .byte 3
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .short 6
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define void @spillSubReg(i64 %arg) #0 {
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bb:
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br i1 undef, label %bb1, label %bb2
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bb1:
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unreachable
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bb2:
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%tmp = load i64* inttoptr (i64 140685446136880 to i64*)
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br i1 undef, label %bb16, label %bb17
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bb16:
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unreachable
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bb17:
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%tmp32 = trunc i64 %tmp to i32
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br i1 undef, label %bb60, label %bb61
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bb60:
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tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
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tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 13, i32 5, i32 %tmp32)
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unreachable
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bb61:
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unreachable
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}
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; Map a single byte subregister. There is no DWARF register number, so
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; we expect the register to be encoded with the proper size and spill offset. We don't know which
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;
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; CHECK-LABEL: .long L{{.*}}-_subRegOffset
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; CHECK-NEXT: .short 0
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; 2 locations
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; CHECK-NEXT: .short 2
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;
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; Check that the subregister operands are 1-byte spills.
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; Location 0: Register, 4-byte, AL
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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;
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; Location 1: Register, 4-byte, BL
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .short 3
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; CHECK-NEXT: .long 0
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define void @subRegOffset(i16 %arg) {
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%v = mul i16 %arg, 5
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%a0 = trunc i16 %v to i8
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tail call void asm sideeffect "nop", "~{bx}"() nounwind
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%arghi = lshr i16 %v, 8
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%a1 = trunc i16 %arghi to i8
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tail call void asm sideeffect "nop", "~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
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tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 14, i32 5, i8 %a0, i8 %a1)
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ret void
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}
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; Map a constant value.
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;
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; CHECK-LABEL: .long L{{.*}}-_liveConstant
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; CHECK-NEXT: .short 0
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; 1 location
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; CHECK-NEXT: .short 1
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; Loc 0: SmallConstant
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 33
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define void @liveConstant() {
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tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 15, i32 5, i32 33)
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ret void
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}
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; Directly map an alloca's address.
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;
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; Callsite 16
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; CHECK-LABEL: .long L{{.*}}-_directFrameIdx
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; CHECK-NEXT: .short 0
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; 1 location
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; CHECK-NEXT: .short 1
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; Loc 0: Direct RBP - ofs
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 6
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; CHECK-NEXT: .long
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; Callsite 17
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; CHECK-LABEL: .long L{{.*}}-_directFrameIdx
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; CHECK-NEXT: .short 0
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; 2 locations
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; CHECK-NEXT: .short 2
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; Loc 0: Direct RBP - ofs
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 6
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; CHECK-NEXT: .long
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; Loc 1: Direct RBP - ofs
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .short 6
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; CHECK-NEXT: .long
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define void @directFrameIdx() {
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entry:
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%metadata1 = alloca i64, i32 3, align 8
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store i64 11, i64* %metadata1
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store i64 12, i64* %metadata1
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store i64 13, i64* %metadata1
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call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 16, i32 0, i64* %metadata1)
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%metadata2 = alloca i8, i32 4, align 8
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%metadata3 = alloca i16, i32 4, align 8
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call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 17, i32 5, i8* null, i32 0, i8* %metadata2, i16* %metadata3)
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ret void
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}
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; Test a 64-bit ID.
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;
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; CHECK: .quad 4294967295
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; CHECK-LABEL: .long L{{.*}}-_longid
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; CHECK: .quad 4294967296
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; CHECK-LABEL: .long L{{.*}}-_longid
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; CHECK: .quad 9223372036854775807
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; CHECK-LABEL: .long L{{.*}}-_longid
|
|
; CHECK: .quad -1
|
|
; CHECK-LABEL: .long L{{.*}}-_longid
|
|
define void @longid() {
|
|
entry:
|
|
tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 4294967295, i32 0, i8* null, i32 0)
|
|
tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 4294967296, i32 0, i8* null, i32 0)
|
|
tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 9223372036854775807, i32 0, i8* null, i32 0)
|
|
tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 -1, i32 0, i8* null, i32 0)
|
|
ret void
|
|
}
|
|
|
|
; Map a value when R11 is the only free register.
|
|
; The scratch register should not be used for a live stackmap value.
|
|
;
|
|
; CHECK-LABEL: .long L{{.*}}-_clobberScratch
|
|
; CHECK-NEXT: .short 0
|
|
; 1 location
|
|
; CHECK-NEXT: .short 1
|
|
; Loc 0: Indirect fp - offset
|
|
; CHECK-NEXT: .byte 3
|
|
; CHECK-NEXT: .byte 4
|
|
; CHECK-NEXT: .short 6
|
|
; CHECK-NEXT: .long -{{[0-9]+}}
|
|
define void @clobberScratch(i32 %a) {
|
|
tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r12},~{r13},~{r14},~{r15}"() nounwind
|
|
tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 16, i32 8, i32 %a)
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.experimental.stackmap(i64, i32, ...)
|
|
declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
|
|
declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
|