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				https://github.com/c64scene-ar/llvm-6502.git
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	We are not working on a DAG and I ran into a number of problems when I enabled the vectorizations of 'diamond-trees' (trees that share leafs). * Imroved the numbering API. * Changed the placement of new instructions to the last root. * Fixed a bug with external tree users with non-zero lane. * Fixed a bug in the placement of in-tree users. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182508 91177308-0d34-0410-b5e6-96231b3b80d8
		
			
				
	
	
		
			48 lines
		
	
	
		
			1.4 KiB
		
	
	
	
		
			LLVM
		
	
	
	
	
	
			
		
		
	
	
			48 lines
		
	
	
		
			1.4 KiB
		
	
	
	
		
			LLVM
		
	
	
	
	
	
; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.7.0"
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;int foo (int *A, int n) {
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;  A[0] += n * 5 + 7;
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;  A[1] += n * 5 + 8;
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;  A[2] += n * 5 + 9;
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;  A[3] += n * 5 + 10;
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;  A[4] += n * 5 + 11;
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;}
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;CHECK: @foo
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;CHECK: load <4 x i32>
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;CHECK: insertelement <4 x i32>
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;CHECK: add <4 x i32>
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;CHECK: store <4 x i32>
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;CHECK: ret
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define i32 @foo(i32* nocapture %A, i32 %n) {
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  %1 = mul nsw i32 %n, 5
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  %2 = add nsw i32 %1, 7
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  %3 = load i32* %A, align 4
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  %4 = add nsw i32 %2, %3
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  store i32 %4, i32* %A, align 4
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  %5 = add nsw i32 %1, 8
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  %6 = getelementptr inbounds i32* %A, i64 1
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  %7 = load i32* %6, align 4
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  %8 = add nsw i32 %5, %7
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  store i32 %8, i32* %6, align 4
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  %9 = add nsw i32 %1, 9
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  %10 = getelementptr inbounds i32* %A, i64 2
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  %11 = load i32* %10, align 4
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  %12 = add nsw i32 %9, %11
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  store i32 %12, i32* %10, align 4
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  %13 = add nsw i32 %1, 10
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  %14 = getelementptr inbounds i32* %A, i64 3
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  %15 = load i32* %14, align 4
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  %16 = add nsw i32 %13, %15
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  store i32 %16, i32* %14, align 4
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  %17 = add nsw i32 %1, 11
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  %18 = getelementptr inbounds i32* %A, i64 4
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  %19 = load i32* %18, align 4
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  %20 = add nsw i32 %17, %19
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  store i32 %20, i32* %18, align 4
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  ret i32 undef
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}
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