Tim Northover 0eb313be18 ARM64: use regalloc-friendly COPY_TO_REGCLASS for bitcasts ... The previous patterns directly inserted FMOV or INS instructions into the DAG for scalar_to_vector & bitconvert patterns. This is horribly inefficient and can generated lots more GPR <-> FPR register traffic than necessary. It's much better to emit instructions the register allocator understands so it can coalesce the copies when appropriate. It led to at least one ISelLowering hack to avoid the problems, which was incorrect for v1i64 (FPR64 has no dsub). It can now be removed entirely. This should also fix PR19331. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205616 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-04 09:03:09 +00:00
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Analysis	Use TopTTI->getGEPCost from within getUserCost	2014-04-01 18:50:06 +00:00
AsmParser
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CodeGen	Make consistent use of MCPhysReg instead of uint16_t throughout the tree.	2014-04-04 05:16:06 +00:00
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ExecutionEngine	Remove section_rel_empty. Just compare begin() and end() instead.	2014-04-03 22:42:22 +00:00
IR	ARM: update subtarget information for Windows on ARM	2014-04-02 20:32:05 +00:00
IRReader
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LTO	Revert "Reapply "LTO: add API to set strategy for -internalize""	2014-04-02 22:05:57 +00:00
MC	Implement getRelocationAddress for MachO and ET_REL elf files.	2014-04-03 23:54:35 +00:00
Object	Add an assert that this is only used with .o files.	2014-04-04 00:31:12 +00:00
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Target	ARM64: use regalloc-friendly COPY_TO_REGCLASS for bitcasts	2014-04-04 09:03:09 +00:00
Transforms	Fix PR19270 - type mismatch caused by invalid optimization.	2014-04-03 17:51:58 +00:00
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