Craig Topper aef361807e [X86] Teach disassembler to handle illegal immediates on AVX512 integer compare instructions. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227302 91177308-0d34-0410-b5e6-96231b3b80d8

2015-01-28 10:09:56 +00:00

..

avx-512.txt

[X86] Teach disassembler to handle illegal immediates on AVX512 integer compare instructions.

2015-01-28 10:09:56 +00:00

fp-stack.txt

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hex-immediates.txt

llvm-mc: Add option for prefering hex format disassembly.

2014-06-11 20:26:40 +00:00

intel-syntax-32.txt

[X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LEA variants in Intel syntax. The memory operand is inherently unsized.

2015-01-08 07:41:30 +00:00

intel-syntax.txt

[X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LEA variants in Intel syntax. The memory operand is inherently unsized.

2015-01-08 07:41:30 +00:00

invalid-VEX-vvvv.txt

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lit.local.cfg

Reduce verbiage of lit.local.cfg files

2014-06-09 22:42:55 +00:00

marked-up.txt

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missing-sib.txt

Test case for r204305.

2014-03-20 06:45:10 +00:00

moffs.txt

[X86] Make the instructions that use AdSize16/32/64 co-exist together without using mode predicates.

2015-01-02 07:02:25 +00:00

padlock.txt

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prefixes.txt

[X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present.

2015-01-03 00:00:20 +00:00

simple-tests.txt

[X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LEA variants in Intel syntax. The memory operand is inherently unsized.

2015-01-08 07:41:30 +00:00

truncated-input.txt

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x86-16.txt

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x86-32.txt

[X86] Convert all the i8imm used by SSE and AVX instructions to u8imm.

2015-01-21 08:15:54 +00:00

x86-64.txt

[X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16.

2015-01-06 08:59:30 +00:00