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0f58dbae4ab2397dc310e19d171a4bc60fc6c9a7
llvm-6502/test/MC
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Akira Hatanaka 0c66403efd [mips] Add definition of JALR instruction which has two register operands. Change the
original JALR instruction with one register operand to be a pseudo-instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 19:48:00 +00:00
..
AArch64
Add AArch64 CRC32 instructions
2013-02-06 09:13:13 +00:00
ARM
Add a special ARM trap encoding for NaCl.
2013-01-30 16:30:19 +00:00
AsmParser
Add support for macro parameters/arguments delimited by spaces,
2012-09-19 20:36:12 +00:00
COFF
[MC][COFF] Delay handling symbol aliases when writing
2013-01-29 22:10:07 +00:00
Disassembler
Add AArch64 CRC32 instructions
2013-02-06 09:13:13 +00:00
ELF
Now that llvm-dwarfdump supports flags to specify which DWARF section to dump,
2013-01-25 21:44:53 +00:00
MachO
Now that llvm-dwarfdump supports flags to specify which DWARF section to dump,
2013-01-25 21:44:53 +00:00
Markup
MC: Simple example parser for MC assembly markup.
2012-10-31 23:24:13 +00:00
MBlaze
Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu
2012-03-25 09:02:19 +00:00
Mips
[mips] Add definition of JALR instruction which has two register operands. Change the
2013-02-07 19:48:00 +00:00
PowerPC
PowerPC: EH adjustments
2013-01-09 17:08:15 +00:00
X86
[MC] Bundle alignment: Invalidate relaxed fragments
2013-02-05 17:55:27 +00:00
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