mirror of
https://github.com/c64scene-ar/llvm-6502.git
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d6cd0381f6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208607 91177308-0d34-0410-b5e6-96231b3b80d8
550 lines
17 KiB
C++
550 lines
17 KiB
C++
//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an AArch64 MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64InstPrinter.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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#define GET_INSTRUCTION_NAME
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#define PRINT_ALIAS_INSTR
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#include "AArch64GenAsmWriter.inc"
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static int64_t unpackSignedImm(int BitWidth, uint64_t Value) {
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assert(!(Value & ~((1ULL << BitWidth)-1)) && "immediate not n-bit");
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if (Value & (1ULL << (BitWidth - 1)))
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return static_cast<int64_t>(Value) - (1LL << BitWidth);
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else
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return Value;
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}
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AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI) :
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MCInstPrinter(MAI, MII, MRI) {
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// Initialize the set of available features.
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setAvailableFeatures(STI.getFeatureBits());
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}
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void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << getRegisterName(RegNo);
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}
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void
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AArch64InstPrinter::printOffsetSImm9Operand(const MCInst *MI,
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unsigned OpNum, raw_ostream &O) {
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const MCOperand &MOImm = MI->getOperand(OpNum);
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int32_t Imm = unpackSignedImm(9, MOImm.getImm());
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O << '#' << Imm;
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}
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void
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AArch64InstPrinter::printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O, unsigned MemSize,
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unsigned RmSize) {
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unsigned ExtImm = MI->getOperand(OpNum).getImm();
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unsigned OptionHi = ExtImm >> 1;
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unsigned S = ExtImm & 1;
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bool IsLSL = OptionHi == 1 && RmSize == 64;
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const char *Ext;
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switch (OptionHi) {
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case 1:
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Ext = (RmSize == 32) ? "uxtw" : "lsl";
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break;
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case 3:
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Ext = (RmSize == 32) ? "sxtw" : "sxtx";
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break;
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default:
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llvm_unreachable("Incorrect Option on load/store (reg offset)");
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}
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O << Ext;
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if (S) {
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unsigned ShiftAmt = Log2_32(MemSize);
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O << " #" << ShiftAmt;
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} else if (IsLSL) {
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O << " #0";
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}
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}
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void
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AArch64InstPrinter::printAddSubImmLSL0Operand(const MCInst *MI,
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unsigned OpNum, raw_ostream &O) {
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const MCOperand &Imm12Op = MI->getOperand(OpNum);
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if (Imm12Op.isImm()) {
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int64_t Imm12 = Imm12Op.getImm();
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assert(Imm12 >= 0 && "Invalid immediate for add/sub imm");
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O << "#" << Imm12;
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} else {
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assert(Imm12Op.isExpr() && "Unexpected shift operand type");
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O << "#" << *Imm12Op.getExpr();
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}
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}
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void
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AArch64InstPrinter::printAddSubImmLSL12Operand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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printAddSubImmLSL0Operand(MI, OpNum, O);
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O << ", lsl #12";
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}
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void
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AArch64InstPrinter::printBareImmOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNum);
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O << MO.getImm();
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}
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template<unsigned RegWidth> void
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AArch64InstPrinter::printBFILSBOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &ImmROp = MI->getOperand(OpNum);
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unsigned LSB = ImmROp.getImm() == 0 ? 0 : RegWidth - ImmROp.getImm();
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O << '#' << LSB;
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}
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void AArch64InstPrinter::printBFIWidthOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &ImmSOp = MI->getOperand(OpNum);
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unsigned Width = ImmSOp.getImm() + 1;
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O << '#' << Width;
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}
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void
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AArch64InstPrinter::printBFXWidthOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &ImmSOp = MI->getOperand(OpNum);
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const MCOperand &ImmROp = MI->getOperand(OpNum - 1);
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unsigned ImmR = ImmROp.getImm();
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unsigned ImmS = ImmSOp.getImm();
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assert(ImmS >= ImmR && "Invalid ImmR, ImmS combination for bitfield extract");
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O << '#' << (ImmS - ImmR + 1);
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}
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void
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AArch64InstPrinter::printCRxOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &CRx = MI->getOperand(OpNum);
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O << 'c' << CRx.getImm();
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}
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void
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AArch64InstPrinter::printCVTFixedPosOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &ScaleOp = MI->getOperand(OpNum);
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O << '#' << (64 - ScaleOp.getImm());
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}
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void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &o) {
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const MCOperand &MOImm8 = MI->getOperand(OpNum);
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assert(MOImm8.isImm()
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&& "Immediate operand required for floating-point immediate inst");
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uint32_t Imm8 = MOImm8.getImm();
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uint32_t Fraction = Imm8 & 0xf;
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uint32_t Exponent = (Imm8 >> 4) & 0x7;
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uint32_t Negative = (Imm8 >> 7) & 0x1;
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float Val = 1.0f + Fraction / 16.0f;
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// That is:
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// 000 -> 2^1, 001 -> 2^2, 010 -> 2^3, 011 -> 2^4,
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// 100 -> 2^-3, 101 -> 2^-2, 110 -> 2^-1, 111 -> 2^0
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if (Exponent & 0x4) {
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Val /= 1 << (7 - Exponent);
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} else {
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Val *= 1 << (Exponent + 1);
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}
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Val = Negative ? -Val : Val;
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o << '#' << format("%.8f", Val);
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}
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void AArch64InstPrinter::printFPZeroOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &o) {
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o << "#0.0";
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}
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void
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AArch64InstPrinter::printCondCodeOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNum);
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O << A64CondCodeToString(static_cast<A64CC::CondCodes>(MO.getImm()));
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}
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void
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AArch64InstPrinter::printInverseCondCodeOperand(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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A64CC::CondCodes CC =
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static_cast<A64CC::CondCodes>(MI->getOperand(OpNum).getImm());
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O << A64CondCodeToString(A64InvertCondCode(CC));
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}
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template <unsigned field_width, unsigned scale> void
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AArch64InstPrinter::printLabelOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNum);
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if (!MO.isImm()) {
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printOperand(MI, OpNum, O);
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return;
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}
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// The immediate of LDR (lit) instructions is a signed 19-bit immediate, which
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// is multiplied by 4 (because all A64 instructions are 32-bits wide).
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uint64_t UImm = MO.getImm();
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uint64_t Sign = UImm & (1LL << (field_width - 1));
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int64_t SImm = scale * ((UImm & ~Sign) - Sign);
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O << "#" << SImm;
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}
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template<unsigned RegWidth> void
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AArch64InstPrinter::printLogicalImmOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNum);
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uint64_t Val;
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A64Imms::isLogicalImmBits(RegWidth, MO.getImm(), Val);
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O << "#0x";
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O.write_hex(Val);
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}
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void
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AArch64InstPrinter::printOffsetUImm12Operand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O, int MemSize) {
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const MCOperand &MOImm = MI->getOperand(OpNum);
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if (MOImm.isImm()) {
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uint32_t Imm = MOImm.getImm() * MemSize;
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O << "#" << Imm;
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} else {
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O << "#" << *MOImm.getExpr();
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}
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}
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void
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AArch64InstPrinter::printShiftOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O,
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A64SE::ShiftExtSpecifiers Shift) {
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const MCOperand &MO = MI->getOperand(OpNum);
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// LSL #0 is not printed
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if (Shift == A64SE::LSL && MO.isImm() && MO.getImm() == 0)
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return;
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switch (Shift) {
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case A64SE::LSL: O << "lsl"; break;
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case A64SE::LSR: O << "lsr"; break;
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case A64SE::ASR: O << "asr"; break;
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case A64SE::ROR: O << "ror"; break;
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default: llvm_unreachable("Invalid shift specifier in logical instruction");
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}
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O << " #" << MO.getImm();
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}
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void
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AArch64InstPrinter::printMoveWideImmOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &UImm16MO = MI->getOperand(OpNum);
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const MCOperand &ShiftMO = MI->getOperand(OpNum + 1);
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if (UImm16MO.isImm()) {
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O << '#' << UImm16MO.getImm();
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if (ShiftMO.getImm() != 0)
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O << ", lsl #" << (ShiftMO.getImm() * 16);
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return;
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}
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O << "#" << *UImm16MO.getExpr();
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}
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void AArch64InstPrinter::printNamedImmOperand(const NamedImmMapper &Mapper,
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const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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bool ValidName;
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const MCOperand &MO = MI->getOperand(OpNum);
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StringRef Name = Mapper.toString(MO.getImm(), ValidName);
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if (ValidName)
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O << Name;
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else
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O << '#' << MO.getImm();
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}
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void
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AArch64InstPrinter::printSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
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const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNum);
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bool ValidName;
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std::string Name = Mapper.toString(MO.getImm(), ValidName);
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if (ValidName) {
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O << Name;
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return;
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}
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}
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void AArch64InstPrinter::printRegExtendOperand(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O,
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A64SE::ShiftExtSpecifiers Ext) {
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// FIXME: In principle TableGen should be able to detect this itself far more
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// easily. We will only accumulate more of these hacks.
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unsigned Reg0 = MI->getOperand(0).getReg();
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unsigned Reg1 = MI->getOperand(1).getReg();
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if (isStackReg(Reg0) || isStackReg(Reg1)) {
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A64SE::ShiftExtSpecifiers LSLEquiv;
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if (Reg0 == AArch64::XSP || Reg1 == AArch64::XSP)
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LSLEquiv = A64SE::UXTX;
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else
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LSLEquiv = A64SE::UXTW;
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if (Ext == LSLEquiv) {
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O << "lsl #" << MI->getOperand(OpNum).getImm();
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return;
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}
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}
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switch (Ext) {
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case A64SE::UXTB: O << "uxtb"; break;
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case A64SE::UXTH: O << "uxth"; break;
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case A64SE::UXTW: O << "uxtw"; break;
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case A64SE::UXTX: O << "uxtx"; break;
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case A64SE::SXTB: O << "sxtb"; break;
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case A64SE::SXTH: O << "sxth"; break;
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case A64SE::SXTW: O << "sxtw"; break;
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case A64SE::SXTX: O << "sxtx"; break;
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default: llvm_unreachable("Unexpected shift type for printing");
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}
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const MCOperand &MO = MI->getOperand(OpNum);
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if (MO.getImm() != 0)
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O << " #" << MO.getImm();
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}
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template<int MemScale> void
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AArch64InstPrinter::printSImm7ScaledOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MOImm = MI->getOperand(OpNum);
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int32_t Imm = unpackSignedImm(7, MOImm.getImm());
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O << "#" << (Imm * MemScale);
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}
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void AArch64InstPrinter::printVPRRegister(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned Reg = MI->getOperand(OpNo).getReg();
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std::string Name = getRegisterName(Reg);
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Name[0] = 'v';
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O << Name;
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}
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void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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unsigned Reg = Op.getReg();
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O << getRegisterName(Reg);
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} else if (Op.isImm()) {
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O << '#' << Op.getImm();
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} else {
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assert(Op.isExpr() && "unknown operand kind in printOperand");
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// If a symbolic branch target was added as a constant expression then print
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// that address in hex.
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const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
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int64_t Address;
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if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
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O << "0x";
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O.write_hex(Address);
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}
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else {
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// Otherwise, just print the expression.
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O << *Op.getExpr();
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}
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}
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}
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void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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StringRef Annot) {
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if (MI->getOpcode() == AArch64::TLSDESCCALL) {
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// This is a special assembler directive which applies an
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// R_AARCH64_TLSDESC_CALL to the following (BLR) instruction. It has a fixed
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// form outside the normal TableGenerated scheme.
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O << "\t.tlsdesccall " << *MI->getOperand(0).getExpr();
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} else if (!printAliasInstr(MI, O))
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printInstruction(MI, O);
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printAnnotation(O, Annot);
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}
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template <A64SE::ShiftExtSpecifiers Ext, bool isHalf>
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void AArch64InstPrinter::printNeonMovImmShiftOperand(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNum);
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assert(MO.isImm() &&
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"Immediate operand required for Neon vector immediate inst.");
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bool IsLSL = false;
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if (Ext == A64SE::LSL)
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IsLSL = true;
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else if (Ext != A64SE::MSL)
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llvm_unreachable("Invalid shift specifier in movi instruction");
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int64_t Imm = MO.getImm();
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// MSL and LSLH accepts encoded shift amount 0 or 1.
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if ((!IsLSL || (IsLSL && isHalf)) && Imm != 0 && Imm != 1)
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llvm_unreachable("Invalid shift amount in movi instruction");
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// LSH accepts encoded shift amount 0, 1, 2 or 3.
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if (IsLSL && (Imm < 0 || Imm > 3))
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llvm_unreachable("Invalid shift amount in movi instruction");
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// Print shift amount as multiple of 8 with MSL encoded shift amount
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// 0 and 1 printed as 8 and 16.
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if (!IsLSL)
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Imm++;
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Imm *= 8;
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// LSL #0 is not printed
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if (IsLSL) {
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if (Imm == 0)
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return;
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O << ", lsl";
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} else
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O << ", msl";
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O << " #" << Imm;
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}
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void AArch64InstPrinter::printNeonUImm0Operand(const MCInst *MI, unsigned OpNum,
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raw_ostream &o) {
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o << "#0x0";
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}
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void AArch64InstPrinter::printUImmHexOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MOUImm = MI->getOperand(OpNum);
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assert(MOUImm.isImm() &&
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"Immediate operand required for Neon vector immediate inst.");
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unsigned Imm = MOUImm.getImm();
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O << "#0x";
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O.write_hex(Imm);
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}
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void AArch64InstPrinter::printUImmBareOperand(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MOUImm = MI->getOperand(OpNum);
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assert(MOUImm.isImm()
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&& "Immediate operand required for Neon vector immediate inst.");
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|
|
unsigned Imm = MOUImm.getImm();
|
|
O << Imm;
|
|
}
|
|
|
|
void AArch64InstPrinter::printNeonUImm64MaskOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MOUImm8 = MI->getOperand(OpNum);
|
|
|
|
assert(MOUImm8.isImm() &&
|
|
"Immediate operand required for Neon vector immediate bytemask inst.");
|
|
|
|
uint32_t UImm8 = MOUImm8.getImm();
|
|
uint64_t Mask = 0;
|
|
|
|
// Replicates 0x00 or 0xff byte in a 64-bit vector
|
|
for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
|
|
if ((UImm8 >> ByteNum) & 1)
|
|
Mask |= (uint64_t)0xff << (8 * ByteNum);
|
|
}
|
|
|
|
O << "#0x";
|
|
O.write_hex(Mask);
|
|
}
|
|
|
|
// If Count > 1, there are two valid kinds of vector list:
|
|
// (1) {Vn.layout, Vn+1.layout, ... , Vm.layout}
|
|
// (2) {Vn.layout - Vm.layout}
|
|
// We choose the first kind as output.
|
|
template <A64Layout::VectorLayout Layout, unsigned Count>
|
|
void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
assert(Count >= 1 && Count <= 4 && "Invalid Number of Vectors");
|
|
|
|
unsigned Reg = MI->getOperand(OpNum).getReg();
|
|
std::string LayoutStr = A64VectorLayoutToString(Layout);
|
|
O << "{ ";
|
|
if (Count > 1) { // Print sub registers separately
|
|
bool IsVec64 = (Layout < A64Layout::VL_16B);
|
|
unsigned SubRegIdx = IsVec64 ? AArch64::dsub_0 : AArch64::qsub_0;
|
|
for (unsigned I = 0; I < Count; I++) {
|
|
std::string Name = getRegisterName(MRI.getSubReg(Reg, SubRegIdx++));
|
|
Name[0] = 'v';
|
|
O << Name << LayoutStr;
|
|
if (I != Count - 1)
|
|
O << ", ";
|
|
}
|
|
} else { // Print the register directly when NumVecs is 1.
|
|
std::string Name = getRegisterName(Reg);
|
|
Name[0] = 'v';
|
|
O << Name << LayoutStr;
|
|
}
|
|
O << " }";
|
|
}
|