mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7a6aa1a391
exact/nsw/nuw shifts and have instcombine infer them when it can prove that the relevant properties are true for a given shift without them. Also, a variety of refactoring to use the new patternmatch logic thrown in for good luck. I believe that this takes care of a bunch of related code quality issues attached to PR8862. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125267 91177308-0d34-0410-b5e6-96231b3b80d8
145 lines
2.8 KiB
LLVM
145 lines
2.8 KiB
LLVM
; RUN: opt < %s -instcombine -S | FileCheck %s
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; CHECK: @sdiv1
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; CHECK: sdiv i32 %x, 8
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define i32 @sdiv1(i32 %x) {
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%y = sdiv i32 %x, 8
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ret i32 %y
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}
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; CHECK: @sdiv2
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; CHECK: ashr exact i32 %x, 3
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define i32 @sdiv2(i32 %x) {
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%y = sdiv exact i32 %x, 8
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ret i32 %y
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}
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; CHECK: @sdiv3
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; CHECK: %y = srem i32 %x, 3
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; CHECK: %z = sub i32 %x, %y
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; CHECK: ret i32 %z
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define i32 @sdiv3(i32 %x) {
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%y = sdiv i32 %x, 3
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%z = mul i32 %y, 3
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ret i32 %z
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}
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; CHECK: @sdiv4
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; CHECK: ret i32 %x
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define i32 @sdiv4(i32 %x) {
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%y = sdiv exact i32 %x, 3
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%z = mul i32 %y, 3
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ret i32 %z
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}
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; CHECK: i32 @sdiv5
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; CHECK: %y = srem i32 %x, 3
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; CHECK: %z = sub i32 %y, %x
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; CHECK: ret i32 %z
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define i32 @sdiv5(i32 %x) {
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%y = sdiv i32 %x, 3
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%z = mul i32 %y, -3
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ret i32 %z
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}
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; CHECK: @sdiv6
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; CHECK: %z = sub i32 0, %x
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; CHECK: ret i32 %z
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define i32 @sdiv6(i32 %x) {
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%y = sdiv exact i32 %x, 3
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%z = mul i32 %y, -3
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ret i32 %z
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}
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; CHECK: @udiv1
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; CHECK: ret i32 %x
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define i32 @udiv1(i32 %x, i32 %w) {
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%y = udiv exact i32 %x, %w
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%z = mul i32 %y, %w
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ret i32 %z
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}
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; CHECK: @udiv2
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; CHECK: %z = lshr exact i32 %x, %w
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; CHECK: ret i32 %z
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define i32 @udiv2(i32 %x, i32 %w) {
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%y = shl i32 1, %w
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%z = udiv exact i32 %x, %y
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ret i32 %z
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}
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; CHECK: @ashr1
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; CHECK: %B = ashr exact i64 %A, 2
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; CHECK: ret i64 %B
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define i64 @ashr1(i64 %X) nounwind {
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%A = shl i64 %X, 8
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%B = ashr i64 %A, 2 ; X/4
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ret i64 %B
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}
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; CHECK: @ashr_icmp
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; CHECK: %B = icmp eq i64 %X, 0
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; CHECK: ret i1 %B
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define i1 @ashr_icmp(i64 %X) nounwind {
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%A = ashr exact i64 %X, 2 ; X/4
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%B = icmp eq i64 %A, 0
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ret i1 %B
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}
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; CHECK: @udiv_icmp1
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; CHECK: icmp ne i64 %X, 0
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define i1 @udiv_icmp1(i64 %X) nounwind {
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%A = udiv exact i64 %X, 5 ; X/5
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%B = icmp ne i64 %A, 0
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ret i1 %B
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}
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; CHECK: @sdiv_icmp1
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; CHECK: icmp eq i64 %X, 0
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define i1 @sdiv_icmp1(i64 %X) nounwind {
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%A = sdiv exact i64 %X, 5 ; X/5 == 0 --> x == 0
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%B = icmp eq i64 %A, 0
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ret i1 %B
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}
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; CHECK: @sdiv_icmp2
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; CHECK: icmp eq i64 %X, 5
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define i1 @sdiv_icmp2(i64 %X) nounwind {
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%A = sdiv exact i64 %X, 5 ; X/5 == 1 --> x == 5
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%B = icmp eq i64 %A, 1
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ret i1 %B
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}
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; CHECK: @sdiv_icmp3
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; CHECK: icmp eq i64 %X, -5
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define i1 @sdiv_icmp3(i64 %X) nounwind {
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%A = sdiv exact i64 %X, 5 ; X/5 == -1 --> x == -5
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%B = icmp eq i64 %A, -1
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ret i1 %B
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}
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; CHECK: @sdiv_icmp4
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; CHECK: icmp eq i64 %X, 0
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define i1 @sdiv_icmp4(i64 %X) nounwind {
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%A = sdiv exact i64 %X, -5 ; X/-5 == 0 --> x == 0
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%B = icmp eq i64 %A, 0
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ret i1 %B
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}
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; CHECK: @sdiv_icmp5
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; CHECK: icmp eq i64 %X, -5
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define i1 @sdiv_icmp5(i64 %X) nounwind {
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%A = sdiv exact i64 %X, -5 ; X/-5 == 1 --> x == -5
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%B = icmp eq i64 %A, 1
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ret i1 %B
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}
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; CHECK: @sdiv_icmp6
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; CHECK: icmp eq i64 %X, 5
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define i1 @sdiv_icmp6(i64 %X) nounwind {
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%A = sdiv exact i64 %X, -5 ; X/-5 == 1 --> x == 5
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%B = icmp eq i64 %A, -1
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ret i1 %B
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}
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